/* * Copyright (C) 2016 BayLibre, SAS * Author: Neil Armstrong * Copyright (C) 2015 Amlogic, Inc. All rights reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, see . */ #include #include #include #include "meson_drv.h" #include "meson_vclk.h" /* * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL. * We handle the following encodings : * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks * * What is missing : * - HDMI Pixel Clocks generation */ /* HHI Registers */ #define HHI_VID_PLL_CLK_DIV 0x1a0 /* 0x68 offset in data sheet */ #define VID_PLL_EN BIT(19) #define VID_PLL_BYPASS BIT(18) #define VID_PLL_PRESET BIT(15) #define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */ #define VCLK2_DIV_MASK 0xff #define VCLK2_DIV_EN BIT(16) #define VCLK2_DIV_RESET BIT(17) #define CTS_VDAC_SEL_MASK (0xf << 28) #define CTS_VDAC_SEL_SHIFT 28 #define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */ #define VCLK2_EN BIT(19) #define VCLK2_SEL_MASK (0x7 << 16) #define VCLK2_SEL_SHIFT 16 #define VCLK2_SOFT_RESET BIT(15) #define VCLK2_DIV1_EN BIT(0) #define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */ #define CTS_ENCI_SEL_MASK (0xf << 28) #define CTS_ENCI_SEL_SHIFT 28 #define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */ #define CTS_ENCI_EN BIT(0) #define CTS_VDAC_EN BIT(4) #define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ #define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ #define HHI_HDMI_PLL_CNTL3 0x328 /* 0xca offset in data sheet */ #define HHI_HDMI_PLL_CNTL4 0x32C /* 0xcb offset in data sheet */ #define HHI_HDMI_PLL_CNTL5 0x330 /* 0xcc offset in data sheet */ #define HHI_HDMI_PLL_CNTL6 0x334 /* 0xcd offset in data sheet */ #define HDMI_PLL_RESET BIT(28) #define HDMI_PLL_LOCK BIT(31) /* * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC * * TOFIX: Refactor into table to also handle HDMI frequency and paths */ static void meson_venci_cvbs_clock_config(struct meson_drm *priv) { unsigned int val; /* Setup PLL to output 1.485GHz */ if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) { regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); } else if (meson_vpu_is_compatible(priv, "amlogic,meson-gxm-vpu") || meson_vpu_is_compatible(priv, "amlogic,meson-gxl-vpu")) { regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729); regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500); /* Reset PLL */ regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HDMI_PLL_RESET, HDMI_PLL_RESET); regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, HDMI_PLL_RESET, 0); } /* Poll for lock bit */ regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, (val & HDMI_PLL_LOCK), 10, 0); /* Disable VCLK2 */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); /* Disable vid_pll output clock */ regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); /* Enable vid_pll bypass to HDMI pll */ regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_BYPASS, VID_PLL_BYPASS); /* Enable the vid_pll output clock */ regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, VID_PLL_EN); /* Setup the VCLK2 divider value to achieve 27MHz */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_MASK, (55 - 1)); /* select vid_pll for vclk2 */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); /* enable vclk2 gate */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); /* select vclk_div1 for enci */ regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT)); /* select vclk_div1 for vdac */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT)); /* release vclk2_div_reset and enable vclk2_div */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN); /* enable vclk2_div1 gate */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_DIV1_EN, VCLK2_DIV1_EN); /* reset vclk2 */ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, VCLK2_SOFT_RESET); regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_SOFT_RESET, 0); /* enable enci_clk */ regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, CTS_ENCI_EN, CTS_ENCI_EN); /* enable vdac_clk */ regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, CTS_VDAC_EN, CTS_VDAC_EN); } void meson_vclk_setup(struct meson_drm *priv, unsigned int target, unsigned int freq) { if (target == MESON_VCLK_TARGET_CVBS && freq == MESON_VCLK_CVBS) meson_venci_cvbs_clock_config(priv); }