/*
 *  BSD LICENSE
 *
 *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    * Redistributions of source code must retain the above copyright
 *      notice, this list of conditions and the following disclaimer.
 *    * Redistributions in binary form must reproduce the above copyright
 *      notice, this list of conditions and the following disclaimer in
 *      the documentation and/or other materials provided with the
 *      distribution.
 *    * Neither the name of Broadcom Corporation nor the names of its
 *      contributors may be used to endorse or promote products derived
 *      from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#include "skeleton.dtsi"

/ {
	compatible = "brcm,nsp";
	model = "Broadcom Northstar Plus SoC";
	interrupt-parent = <&gic>;

	mpcore {
		compatible = "simple-bus";
		ranges = <0x00000000 0x19020000 0x00003000>;
		#address-cells = <1>;
		#size-cells = <1>;

		cpus {
			#address-cells = <1>;
			#size-cells = <0>;

			cpu@0 {
				device_type = "cpu";
				compatible = "arm,cortex-a9";
				next-level-cache = <&L2>;
				reg = <0x0>;
			};
		};

		timer@0200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x0200 0x100>;
			interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&periph_clk>;
		};

		twd-timer@0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x0600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&periph_clk>;
		};

		twd-watchdog@0620 {
			compatible = "arm,cortex-a9-twd-wdt";
			reg = <0x0620 0x20>;
			interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
						  IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&periph_clk>;
		};

		gic: interrupt-controller@1000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x1000 0x1000>,
			      <0x0100 0x100>;
		};

		L2: l2-cache {
			compatible = "arm,pl310-cache";
			reg = <0x2000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		periph_clk: periph_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <500000000>;
		};
	};

	axi {
		compatible = "simple-bus";
		ranges = <0x00000000 0x18000000 0x0011ba08>;
		#address-cells = <1>;
		#size-cells = <1>;

		uart0: serial@0300 {
			compatible = "ns16550a";
			reg = <0x0300 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <62499840>;
			status = "disabled";
		};

		uart1: serial@0400 {
			compatible = "ns16550a";
			reg = <0x0400 0x100>;
			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
			clock-frequency = <62499840>;
			status = "disabled";
		};

		pcie0: pcie@12000 {
			compatible = "brcm,iproc-pcie";
			reg = <0x12000 0x1000>;

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_NONE>;

			linux,pci-domain = <0>;

			bus-range = <0x00 0xff>;

			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";

			/* Note: The HW does not support I/O resources.  So,
			 * only the memory resource range is being specified.
			 */
			ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;

			status = "disabled";
		};

		pcie1: pcie@13000 {
			compatible = "brcm,iproc-pcie";
			reg = <0x13000 0x1000>;

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 137 IRQ_TYPE_NONE>;

			linux,pci-domain = <1>;

			bus-range = <0x00 0xff>;

			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";

			/* Note: The HW does not support I/O resources.  So,
			 * only the memory resource range is being specified.
			 */
			ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;

			status = "disabled";
		};

		pcie2: pcie@14000 {
			compatible = "brcm,iproc-pcie";
			reg = <0x14000 0x1000>;

			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 143 IRQ_TYPE_NONE>;

			linux,pci-domain = <2>;

			bus-range = <0x00 0xff>;

			#address-cells = <3>;
			#size-cells = <2>;
			device_type = "pci";

			/* Note: The HW does not support I/O resources.  So,
			 * only the memory resource range is being specified.
			 */
			ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;

			status = "disabled";
		};

		nand: nand@26000 {
			compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
			reg = <0x026000 0x600>,
			      <0x11b408 0x600>,
			      <0x026f00 0x20>;
			reg-names = "nand", "iproc-idm", "iproc-ext";
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;

			#address-cells = <1>;
			#size-cells = <0>;

			brcm,nand-has-wp;
		};

		i2c0: i2c@38000 {
			compatible = "brcm,iproc-i2c";
			reg = <0x38000 0x50>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <GIC_SPI 89 IRQ_TYPE_NONE>;
			clock-frequency = <100000>;
		};
	};
};