// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016 Freescale Semiconductor, Inc.
 * Copyright 2017-2018 NXP
 *   Dong Aisheng <aisheng.dong@nxp.com>
 */

#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "imx7ulp-pinfunc.h"

/ {
	interrupt-parent = <&intc>;

	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		gpio0 = &gpio_ptc;
		gpio1 = &gpio_ptd;
		gpio2 = &gpio_pte;
		gpio3 = &gpio_ptf;
		i2c0 = &lpi2c6;
		i2c1 = &lpi2c7;
		mmc0 = &usdhc0;
		mmc1 = &usdhc1;
		serial0 = &lpuart4;
		serial1 = &lpuart5;
		serial2 = &lpuart6;
		serial3 = &lpuart7;
		usbphy0 = &usbphy1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@f00 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0xf00>;
			operating-points = <
				/* KHz	uV */
				720000	1125000
				500210	1025000
			>;
			clocks = <&smc1 IMX7ULP_CLK_ARM>,
				 <&scg1 IMX7ULP_CLK_CORE_DIV>,
				 <&scg1 IMX7ULP_CLK_SYS_SEL>,
				 <&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>,
				 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>,
				 <&scg1 IMX7ULP_CLK_SPLL_PFD0>,
				 <&scg1 IMX7ULP_CLK_SPLL_SEL>,
				 <&scg1 IMX7ULP_CLK_FIRC>,
				 <&scg1 IMX7ULP_CLK_SPLL>;
			clock-names = "arm", "core_div", "sys_sel", "hsrun_sys_sel",
				      "hsrun_core", "spll_pfd0", "spll_sel", "firc",
				      "spll";
		};
	};

        reserved-memory {
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;

                /* global autoconfigured region for contiguous allocations */
                linux,cma {
                        compatible = "shared-dma-pool";
                        reusable;
                        size = <0xC000000>;
                        alignment = <0x2000>;
                        linux,cma-default;
                };
        };

	intc: interrupt-controller@40021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x40021000 0x1000>,
		      <0x40022000 0x1000>;
	};

	rosc: clock-rosc {
		compatible = "fixed-clock";
		clock-frequency = <32768>;
		clock-output-names = "rosc";
		#clock-cells = <0>;
	};

	sosc: clock-sosc {
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
		clock-output-names = "sosc";
		#clock-cells = <0>;
	};

	sirc: clock-sirc {
		compatible = "fixed-clock";
		clock-frequency = <16000000>;
		clock-output-names = "sirc";
		#clock-cells = <0>;
	};

	firc: clock-firc {
		compatible = "fixed-clock";
		clock-frequency = <48000000>;
		clock-output-names = "firc";
		#clock-cells = <0>;
	};

	upll: clock-upll {
		compatible = "fixed-clock";
		clock-frequency = <480000000>;
		clock-output-names = "upll";
		#clock-cells = <0>;
	};

	sram: sram@20000000 {
		compatible = "fsl,lpm-sram";
		reg = <0x1fffc000 0x4000>;
	};

	caam_sm: caam-sm@26000000 {
		 compatible = "fsl,imx6q-caam-sm";
		 reg = <0x26000000 0x8000>;
	};

	ahbbridge0: bus@40000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x40000000 0x800000>;
		ranges;

		edma1: dma-controller@40080000 {
			#dma-cells = <2>;
			compatible = "fsl,imx7ulp-edma";
			reg = <0x40080000 0x2000>,
				<0x40210000 0x1000>;
			dma-channels = <32>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clock-names = "dma", "dmamux0";
			clocks = <&pcc2 IMX7ULP_CLK_DMA1>,
				 <&pcc2 IMX7ULP_CLK_DMA_MUX1>;
		};

		mu: mu@40220000 {
			compatible = "fsl,imx7ulp-mu";
			reg = <0x40220000 0x1000>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			#mbox-cells = <2>;
		};

		nmi: nmi@40220000 {
			compatible = "fsl,imx7ulp-nmi";
			reg = <0x40220000 0x1000>;
			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
			status = "okay";
		};

		mu_lp: mu_lp@40220000 {
			compatible = "fsl,imx7ulp-mu-lp", "fsl,imx6sx-mu-lp";
			reg = <0x40220000 0x1000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
					<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			status = "okay";
		};

		lpspi2: spi@40290000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx7ulp-spi";
			reg = <0x40290000 0x10000>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPSPI2>,
				 <&pcc2 IMX7ULP_CLK_DUMMY>;
			clock-names = "per", "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPSPI2>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
			dmas = <&edma1 0 26>, <&edma1 0 25>;
			dma-names = "tx","rx";
			status = "disabled";
		};

		lpspi3: spi@402A0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "fsl,imx7ulp-spi";
			reg = <0x402A0000 0x10000>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPSPI3>,
				 <&pcc2 IMX7ULP_CLK_DUMMY>;
			clock-names = "per", "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPSPI3>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
			dmas = <&edma1 0 28>, <&edma1 0 27>;
			dma-names = "tx","rx";
			status = "disabled";
		};

		crypto: crypto@40240000 {
			compatible = "fsl,sec-v4.0";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40240000 0x10000>;
			ranges = <0 0x40240000 0x10000>;
			clocks = <&pcc2 IMX7ULP_CLK_CAAM>,
				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
			clock-names = "aclk", "ipg";

			sec_jr0: jr0@1000 {
				compatible = "fsl,sec-v4.0-job-ring";
				reg = <0x1000 0x1000>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			};

			sec_jr1: jr1@2000 {
				compatible = "fsl,sec-v4.0-job-ring";
				reg = <0x2000 0x1000>;
				interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		lpi2c4: lpi2c4@402b0000 {
			compatible = "fsl,imx7ulp-lpi2c";
			reg = <0x402b0000 0x10000>;
			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPI2C4>,
				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
			clock-names = "per", "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPI2C4>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpi2c5: lpi2c5@402c0000 {
			compatible = "fsl,imx7ulp-lpi2c";
			reg = <0x402c0000 0x10000>;
			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPI2C5>,
				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
			clock-names = "per", "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPI2C5>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
		};

		lpuart4: serial@402d0000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x402d0000 0x1000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
			clock-names = "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
			assigned-clock-rates = <24000000>;
			status = "disabled";
		};

		lpuart5: serial@402e0000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x402e0000 0x1000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
			clock-names = "ipg";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
			dmas = <&edma1 0 20>, <&edma1 0 19>;
			dma-names = "tx","rx";
			status = "disabled";
		};

		tpm4: pwm@40250000 {
			compatible = "fsl,imx7ulp-pwm";
			reg = <0x40250000 0x1000>;
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
			clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		tpm5: tpm@40260000 {
			compatible = "fsl,imx7ulp-tpm";
			reg = <0x40260000 0x1000>;
			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&pcc2 IMX7ULP_CLK_LPTPM5>;
			clock-names = "ipg", "per";
		};

		usbotg1: usb@40330000 {
			compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb";
			reg = <0x40330000 0x200>;
			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_USB0>;
			phys = <&usbphy1>;
			fsl,usbmisc = <&usbmisc1 0>;
			ahb-burst-config = <0x0>;
			tx-burst-size-dword = <0x8>;
			rx-burst-size-dword = <0x8>;
			status = "disabled";
		};

		usbmisc1: usbmisc@40330200 {
			compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc";
			#index-cells = <1>;
			reg = <0x40330200 0x200>;
		};

		usbphy1: usb-phy@40350000 {
			compatible = "fsl,imx7ulp-usbphy", "fsl,imx6ul-usbphy";
			reg = <0x40350000 0x1000>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_USB_PHY>;
			#phy-cells = <0>;
			nxp,sim = <&sim>;
		};

		usdhc0: mmc@40370000 {
			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
			reg = <0x40370000 0x10000>;
			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&pcc2 IMX7ULP_CLK_USDHC0>;
			clock-names = "ipg", "ahb", "per";
			assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD1>, <&pcc2 IMX7ULP_CLK_USDHC0>;
			assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD1>;
			assigned-clock-rates = <0>, <352800000>;
			bus-width = <4>;
			fsl,tuning-start-tap = <20>;
			fsl,tuning-step = <2>;
			status = "disabled";
		};

		usdhc1: mmc@40380000 {
			compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
			reg = <0x40380000 0x10000>;
			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&pcc2 IMX7ULP_CLK_USDHC1>;
			clock-names = "ipg", "ahb", "per";
			assigned-clocks = <&scg1 IMX7ULP_CLK_APLL_PFD1>, <&pcc2 IMX7ULP_CLK_USDHC1>;
			assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD1>;
			assigned-clock-rates = <0>, <352800000>;
			bus-width = <4>;
			fsl,tuning-start-tap = <20>;
			fsl,tuning-step = <2>;
			status = "disabled";
		};

		scg1: clock-controller@403e0000 {
			compatible = "fsl,imx7ulp-scg1";
			reg = <0x403e0000 0x10000>;
			clocks = <&rosc>, <&sosc>, <&sirc>,
				 <&firc>, <&upll>;
			clock-names = "rosc", "sosc", "sirc",
				      "firc", "upll";
			#clock-cells = <1>;
		};

		wdog1: wdog@403D0000 {
			compatible = "fsl,imx7ulp-wdt";
			reg = <0x403D0000 0x10000>;
			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
			assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
			assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			/*
			 * As the 1KHz LPO clock rate is not trimed,the actually clock
			 * is about 667Hz, so the init timeout 60s should set 40*1000
			 * in the TOVAL register.
			 */
			timeout-sec = <40>;
		};

		wdog2: wdog@40430000 {
			compatible = "fsl,imx7ulp-wdt";
			reg = <0x40430000 0x10000>;
			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
			assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
			assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			timeout-sec = <40>;
		};

		pcc2: clock-controller@403f0000 {
			compatible = "fsl,imx7ulp-pcc2";
			reg = <0x403f0000 0x10000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
				 <&scg1 IMX7ULP_CLK_UPLL>,
				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_ROSC>,
				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
				      "upll", "sosc_bus_clk",
				      "firc_bus_clk", "rosc", "spll_bus_clk";
			assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
		};

		pmc1: pmc1@40400000 {
			compatible = "fsl,imx7ulp-pmc1";
			reg = <0x40400000 0x1000>;
		};

		smc1: clock-controller@40410000 {
			compatible = "fsl,imx7ulp-smc1";
			reg = <0x40410000 0x1000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
				 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
			clock-names = "divcore", "hsrun_divcore";
		};

		pcc3: clock-controller@40b30000 {
			compatible = "fsl,imx7ulp-pcc3";
			reg = <0x40b30000 0x10000>;
			#clock-cells = <1>;
			clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
				 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
				 <&scg1 IMX7ULP_CLK_DDR_DIV>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
				 <&scg1 IMX7ULP_CLK_UPLL>,
				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
				 <&scg1 IMX7ULP_CLK_ROSC>,
				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
			clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
				      "upll", "sosc_bus_clk",
				      "firc_bus_clk", "rosc", "spll_bus_clk";
		};
	};

	ahbbridge1: bus@40800000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x40800000 0x800000>;
		ranges;

		lpi2c6: i2c@40a40000 {
			compatible = "fsl,imx7ulp-lpi2c";
			reg = <0x40a40000 0x10000>;
			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>,
				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
			clock-names = "per", "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpi2c7: i2c@40a50000 {
			compatible = "fsl,imx7ulp-lpi2c";
			reg = <0x40a50000 0x10000>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>,
				 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
			clock-names = "per", "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
			status = "disabled";
		};

		lpuart6: serial@40a60000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x40a60000 0x1000>;
			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
			clock-names = "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
			dmas = <&edma1 0 22>, <&edma1 0 21>;
			dma-names = "tx","rx";
			status = "disabled";
		};

		lpuart7: serial@40a70000 {
			compatible = "fsl,imx7ulp-lpuart";
			reg = <0x40a70000 0x1000>;
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3  IMX7ULP_CLK_LPUART7>;
			clock-names = "ipg";
			assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
			assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
			assigned-clock-rates = <48000000>;
			dmas = <&edma1 0 24>, <&edma1 0 23>;
			dma-names = "tx","rx";
			status = "disabled";
		};

		mipi_dsi: mipi_dsi@40a90000 {
			compatible = "fsl,imx7ulp-mipi-dsi";
			reg = <0x40a90000 0x1000>;
			interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&pcc3 IMX7ULP_CLK_DSI>;
			clock-names = "mipi_dsi_clk";
			data-lanes-num = <2>;
			phy-ref-clkfreq = <24000000>;
			max-data-rate  = <800000000>;
			sim = <&sim>;
			status = "disabled";
		};

		lcdif: lcdif@40aa0000 {
			compatible = "fsl,imx7ulp-lcdif";
			reg = <0x40aa0000 0x1000>;
			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&scg1 IMX7ULP_CLK_DUMMY>,
				 <&pcc3 IMX7ULP_CLK_LCDIF>,
				 <&scg1 IMX7ULP_CLK_DUMMY>;
			clock-names = "axi", "pix", "disp_axi";
			status = "disabled";
		};

		memory-controller@40ab0000 {
			compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
			reg = <0x40ab0000 0x1000>;
			clocks = <&pcc3 IMX7ULP_CLK_MMDC>;
		};

		iomuxc1: pinctrl@40ac0000 {
			compatible = "fsl,imx7ulp-iomuxc1";
			reg = <0x40ac0000 0x1000>;
		};

		gpio_ptc: gpio@40ae0000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40ae0000 0x1000 0x400f0000 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLC>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 0 20>;
		};

		gpio_ptd: gpio@40af0000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40af0000 0x1000 0x400f0040 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLD>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 32 12>;
		};

		gpio_pte: gpio@40b00000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40b00000 0x1000 0x400f0080 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLE>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 64 16>;
		};

		gpio_ptf: gpio@40b10000 {
			compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
			reg = <0x40b10000 0x1000 0x400f00c0 0x40>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pcc2 IMX7ULP_CLK_RGPIO2P1>,
				 <&pcc3 IMX7ULP_CLK_PCTLF>;
			clock-names = "gpio", "port";
			gpio-ranges = <&iomuxc1 0 96 20>;
		};

		gpu: gpu@41800000 {
			compatible = "fsl,imx7ulp-gpu", "fsl,imx6q-gpu";
			reg = <0x41800000 0x80000>, <0x41880000 0x80000>,
				<0x60000000 0x40000000>, <0x0 0x4000000>;
			reg-names = "iobase_3d", "iobase_2d",
				"phys_baseaddr", "contiguous_mem";
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "irq_3d", "irq_2d";
			clocks = <&pcc3 IMX7ULP_CLK_GPU3D>,
				<&scg1 IMX7ULP_CLK_DUMMY>,
				<&scg1 IMX7ULP_CLK_GPU_DIV>,
				<&pcc3 IMX7ULP_CLK_GPU2D>,
				<&scg1 IMX7ULP_CLK_NIC1_DIV>;
			clock-names = "gpu3d_clk", "gpu3d_shader_clk",
				"gpu3d_axi_clk", "gpu2d_clk",
				"gpu2d_axi_clk";
			assigned-clocks =  <&scg1 IMX7ULP_CLK_APLL_PFD2>, <&pcc3 IMX7ULP_CLK_GPU3D>, <&pcc3 IMX7ULP_CLK_GPU2D>;
			assigned-clock-parents = <0>, <&scg1 IMX7ULP_CLK_APLL_PFD2>, <&scg1 IMX7ULP_CLK_APLL_PFD2>;
			assigned-clock-rates = <400000000>, <400000000>, <400000000>;
		};
	};

	m4aips1: bus@41080000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		reg = <0x41080000 0x80000>;
		ranges;

		pmc0: pmc0@410a1000 {
			compatible = "fsl,imx7ulp-pmc0";
			reg = <0x410a1000 0x1000>;
		};

		sim: sim@410a3000 {
			compatible = "fsl,imx7ulp-sim", "syscon";
			reg = <0x410a3000 0x1000>;
		};

		ocotp: ocotp-ctrl@410a6000 {
			compatible = "fsl,imx7ulp-ocotp", "syscon";
			reg = <0x410a6000 0x4000>;
			clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
		};
	};

	rpmsg: rpmsg{
		compatible = "fsl,imx7ulp-rpmsg";
		/* up to now, the following channels are used in imx rpmsg
		 * - tx1/rx1: messages channel.
		 * - general interrupt1: remote proc finish re-init rpmsg stack
		 *   when A core is partition reset.
		 */
		mbox-names = "tx", "rx", "rxdb";
		mboxes = <&mu 0 1
			  &mu 1 1
			  &mu 3 1>;
		status = "disabled";
	};

        heartbeat-rpmsg {
		compatible = "fsl,heartbeat-rpmsg";
	};

	rtc-rpmsg {
		compatible = "fsl,imx-rpmsg-rtc";
	};

};