58 lines
2.0 KiB
Plaintext
58 lines
2.0 KiB
Plaintext
* NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock bindings
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The Low-Power Clock Gate (LPCG) modules contain a local programming
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model to control the clock gates for the peripherals. An LPCG module
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is used to locally gate the clocks for the associated peripheral.
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Note:
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This level of clock gating is provided after the clocks are generated
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by the SCU resources and clock controls. Thus even if the clock is
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enabled by these control bits, it might still not be running based
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on the base resource.
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Required properties:
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- compatible: Should be one of:
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"fsl,imx8qxp-lpcg"
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"fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg".
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- reg: Address and length of the register set.
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- #clock-cells: Should be 1. One LPCG supports multiple clocks.
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- clocks: Input parent clocks phandle array for each clock.
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- bit-offset: An integer array indicating the bit offset for each clock.
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- hw-autogate: Boolean array indicating whether supports HW autogate for
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each clock.
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- clock-output-names: Shall be the corresponding names of the outputs.
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NOTE this property must be specified in the same order
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as the clock bit-offset and hw-autogate property.
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- power-domains: Should contain the power domain used by this clock.
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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Examples:
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#include <dt-bindings/clock/imx8qxp-clock.h>
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sdhc0_lpcg: clock-controller@5b200000 {
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compatible = "fsl,imx8qxp-lpcg";
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reg = <0x5b200000 0x10000>;
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#clock-cells = <1>;
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clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>,
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<&conn_ipg_clk>, <&conn_axi_clk>;
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bit-offset = <0 16 20>;
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clock-output-names = "sdhc0_lpcg_per_clk",
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"sdhc0_lpcg_ipg_clk",
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"sdhc0_lpcg_ahb_clk";
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power-domains = <&pd IMX_SC_R_SDHC_0>;
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};
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usdhc1: mmc@5b010000 {
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compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x5b010000 0x10000>;
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clocks = <&sdhc0_lpcg 1>,
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<&sdhc0_lpcg 0>,
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<&sdhc0_lpcg 2>;
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clock-names = "ipg", "per", "ahb";
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};
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