20 lines
560 B
Plaintext
20 lines
560 B
Plaintext
Xilinx Zynq FPGA Manager
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Required properties:
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- compatible: should contain "xlnx,zynq-devcfg-1.0"
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- reg: base address and size for memory mapped io
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- interrupts: interrupt for the FPGA manager device
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- clocks: phandle for clocks required operation
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- clock-names: name for the clock, should be "ref_clk"
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- syscon: phandle for access to SLCR registers
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Example:
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devcfg: devcfg@f8007000 {
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compatible = "xlnx,zynq-devcfg-1.0";
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reg = <0xf8007000 0x100>;
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interrupts = <0 8 4>;
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clocks = <&clkc 12>;
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clock-names = "ref_clk";
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syscon = <&slcr>;
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};
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