773 lines
20 KiB
C
773 lines
20 KiB
C
/*
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* Copyright (C) 2011-2016 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/*!
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* @file busfreq_ddr3.c
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*
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* @brief iMX6 DDR3 frequency change specific file.
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*
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* @ingroup PM
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*/
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#include <asm/cacheflush.h>
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#include <asm/fncpy.h>
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#include <asm/io.h>
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#include <asm/mach/map.h>
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#include <asm/mach-types.h>
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#include <asm/tlb.h>
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#include <linux/busfreq-imx.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/cpumask.h>
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#include <linux/delay.h>
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#include <linux/genalloc.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/proc_fs.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include "hardware.h"
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#include "common.h"
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#define SMP_WFE_CODE_SIZE 0x400
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#define MIN_DLL_ON_FREQ 333000000
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#define MAX_DLL_OFF_FREQ 125000000
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#define MMDC0_MPMUR0 0x8b8
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#define MMDC0_MPMUR0_OFFSET 16
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#define MMDC0_MPMUR0_MASK 0x3ff
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/*
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* This structure is for passing necessary data for low level ocram
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* busfreq code(arch/arm/mach-imx/ddr3_freq_imx6.S), if this struct
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* definition is changed, the offset definition in
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* arch/arm/mach-imx/ddr3_freq_imx6.S must be also changed accordingly,
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* otherwise, the busfreq change function will be broken!
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*
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* This structure will be placed in front of the asm code on ocram.
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*/
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struct imx6_busfreq_info {
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u32 freq;
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void *ddr_settings;
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u32 dll_off;
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void *iomux_offsets;
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u32 mu_delay_val;
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} __aligned(8);
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static struct imx6_busfreq_info *imx6_busfreq_info;
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/* DDR settings */
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static unsigned long (*iram_ddr_settings)[2];
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static unsigned long (*normal_mmdc_settings)[2];
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static unsigned long (*iram_iomux_settings)[2];
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static void __iomem *mmdc_base;
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static void __iomem *iomux_base;
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static void __iomem *gic_dist_base;
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static int ddr_settings_size;
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static int iomux_settings_size;
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static int curr_ddr_rate;
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void (*imx6_up_change_ddr_freq)(struct imx6_busfreq_info *busfreq_info);
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extern void imx6_up_ddr3_freq_change(struct imx6_busfreq_info *busfreq_info);
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void (*imx7d_change_ddr_freq)(u32 freq) = NULL;
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extern void imx7d_ddr3_freq_change(u32 freq);
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extern void imx_lpddr3_freq_change(u32 freq);
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void (*mx6_change_ddr_freq)(u32 freq, void *ddr_settings,
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bool dll_mode, void *iomux_offsets) = NULL;
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extern unsigned int ddr_normal_rate;
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extern int low_bus_freq_mode;
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extern int audio_bus_freq_mode;
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extern void mx6_ddr3_freq_change(u32 freq, void *ddr_settings,
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bool dll_mode, void *iomux_offsets);
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extern unsigned long save_ttbr1(void);
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extern void restore_ttbr1(unsigned long ttbr1);
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extern unsigned long ddr_freq_change_iram_base;
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extern unsigned long ddr_freq_change_total_size;
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extern unsigned long iram_tlb_phys_addr;
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extern unsigned long mx6_ddr3_freq_change_start asm("mx6_ddr3_freq_change_start");
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extern unsigned long mx6_ddr3_freq_change_end asm("mx6_ddr3_freq_change_end");
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extern unsigned long imx6_up_ddr3_freq_change_start asm("imx6_up_ddr3_freq_change_start");
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extern unsigned long imx6_up_ddr3_freq_change_end asm("imx6_up_ddr3_freq_change_end");
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#ifdef CONFIG_SMP
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static unsigned long wfe_freq_change_iram_base;
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volatile u32 *wait_for_ddr_freq_update;
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static unsigned int online_cpus;
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static u32 *irqs_used;
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void (*wfe_change_ddr_freq)(u32 cpuid, u32 *ddr_freq_change_done);
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void (*imx7_wfe_change_ddr_freq)(u32 cpuid, u32 ocram_base);
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extern void wfe_smp_freq_change(u32 cpuid, u32 *ddr_freq_change_done);
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extern void imx7_smp_wfe(u32 cpuid, u32 ocram_base);
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extern unsigned long wfe_smp_freq_change_start asm("wfe_smp_freq_change_start");
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extern unsigned long wfe_smp_freq_change_end asm("wfe_smp_freq_change_end");
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extern void __iomem *scu_base;
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#endif
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unsigned long ddr3_dll_mx6sx[][2] = {
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{0x0c, 0x0},
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{0x10, 0x0},
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{0x1C, 0x04008032},
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{0x1C, 0x00048031},
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{0x1C, 0x05208030},
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{0x1C, 0x04008040},
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{0x818, 0x0},
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{0x18, 0x0},
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};
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unsigned long ddr3_calibration_mx6sx[][2] = {
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{0x83c, 0x0},
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{0x840, 0x0},
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{0x848, 0x0},
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{0x850, 0x0},
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};
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unsigned long iomux_offsets_mx6sx[][2] = {
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{0x330, 0x0},
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{0x334, 0x0},
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{0x338, 0x0},
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{0x33c, 0x0},
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};
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unsigned long iomux_offsets_mx6ul[][2] = {
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{0x280, 0x0},
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{0x284, 0x0},
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};
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unsigned long ddr3_dll_mx6q[][2] = {
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{0x0c, 0x0},
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{0x10, 0x0},
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{0x1C, 0x04088032},
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{0x1C, 0x0408803a},
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{0x1C, 0x08408030},
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{0x1C, 0x08408038},
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{0x818, 0x0},
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{0x18, 0x0},
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};
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unsigned long ddr3_calibration[][2] = {
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{0x83c, 0x0},
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{0x840, 0x0},
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{0x483c, 0x0},
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{0x4840, 0x0},
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{0x848, 0x0},
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{0x4848, 0x0},
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{0x850, 0x0},
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{0x4850, 0x0},
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};
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unsigned long iomux_offsets_mx6q[][2] = {
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{0x5A8, 0x0},
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{0x5B0, 0x0},
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{0x524, 0x0},
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{0x51C, 0x0},
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{0x518, 0x0},
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{0x50C, 0x0},
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{0x5B8, 0x0},
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{0x5C0, 0x0},
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};
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unsigned long ddr3_dll_mx6dl[][2] = {
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{0x0c, 0x0},
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{0x10, 0x0},
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{0x1C, 0x04008032},
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{0x1C, 0x0400803a},
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{0x1C, 0x07208030},
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{0x1C, 0x07208038},
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{0x818, 0x0},
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{0x18, 0x0},
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};
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unsigned long iomux_offsets_mx6dl[][2] = {
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{0x4BC, 0x0},
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{0x4C0, 0x0},
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{0x4C4, 0x0},
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{0x4C8, 0x0},
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{0x4CC, 0x0},
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{0x4D0, 0x0},
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{0x4D4, 0x0},
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{0x4D8, 0x0},
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};
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int can_change_ddr_freq(void)
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{
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return 1;
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}
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#ifdef CONFIG_SMP
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/*
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* each active core apart from the one changing
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* the DDR frequency will execute this function.
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* the rest of the cores have to remain in WFE
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* state until the frequency is changed.
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*/
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static irqreturn_t wait_in_wfe_irq(int irq, void *dev_id)
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{
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u32 me;
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me = smp_processor_id();
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#ifdef CONFIG_LOCAL_TIMERS
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER,
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&me);
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#endif
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if (cpu_is_imx7d())
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imx7_wfe_change_ddr_freq(0x8 * me,
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(u32)ddr_freq_change_iram_base);
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else
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wfe_change_ddr_freq(0xff << (me * 8),
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(u32 *)&iram_iomux_settings[0][1]);
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#ifdef CONFIG_LOCAL_TIMERS
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT,
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&me);
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#endif
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return IRQ_HANDLED;
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}
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#endif
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/* change the DDR frequency. */
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int update_ddr_freq_imx_smp(int ddr_rate)
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{
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int me = 0;
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unsigned long ttbr1;
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bool dll_off = false;
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int i;
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#ifdef CONFIG_SMP
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unsigned int reg = 0;
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int cpu = 0;
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#endif
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int mode = get_bus_freq_mode();
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if (!can_change_ddr_freq())
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return -1;
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if (ddr_rate == curr_ddr_rate)
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return 0;
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printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate);
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if (cpu_is_imx6()) {
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if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO))
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dll_off = true;
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iram_ddr_settings[0][0] = ddr_settings_size;
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iram_iomux_settings[0][0] = iomux_settings_size;
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if (ddr_rate == ddr_normal_rate) {
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for (i = 0; i < iram_ddr_settings[0][0]; i++) {
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iram_ddr_settings[i + 1][0] =
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normal_mmdc_settings[i][0];
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iram_ddr_settings[i + 1][1] =
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normal_mmdc_settings[i][1];
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}
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}
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}
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/* ensure that all Cores are in WFE. */
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local_irq_disable();
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#ifdef CONFIG_SMP
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me = smp_processor_id();
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/* Make sure all the online cores are active */
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while (1) {
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bool not_exited_busfreq = false;
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u32 reg = 0;
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for_each_online_cpu(cpu) {
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if (cpu_is_imx7d())
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reg = *(wait_for_ddr_freq_update + 1);
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else if (cpu_is_imx6())
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reg = __raw_readl(scu_base + 0x08);
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if (reg & (0x02 << (cpu * 8)))
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not_exited_busfreq = true;
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}
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if (!not_exited_busfreq)
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break;
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}
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wmb();
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*wait_for_ddr_freq_update = 1;
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dsb();
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if (cpu_is_imx7d())
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online_cpus = *(wait_for_ddr_freq_update + 1);
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else if (cpu_is_imx6())
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online_cpus = readl_relaxed(scu_base + 0x08);
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for_each_online_cpu(cpu) {
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*((char *)(&online_cpus) + (u8)cpu) = 0x02;
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if (cpu != me) {
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/* set the interrupt to be pending in the GIC. */
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reg = 1 << (irqs_used[cpu] % 32);
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writel_relaxed(reg, gic_dist_base + GIC_DIST_PENDING_SET
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+ (irqs_used[cpu] / 32) * 4);
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}
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}
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/* Wait for the other active CPUs to idle */
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while (1) {
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u32 reg = 0;
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if (cpu_is_imx7d())
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reg = *(wait_for_ddr_freq_update + 1);
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else if (cpu_is_imx6())
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reg = readl_relaxed(scu_base + 0x08);
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reg |= (0x02 << (me * 8));
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if (reg == online_cpus)
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break;
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}
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#endif
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/* Ensure iram_tlb_phys_addr is flushed to DDR. */
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__cpuc_flush_dcache_area(&iram_tlb_phys_addr,
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sizeof(iram_tlb_phys_addr));
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if (cpu_is_imx6())
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outer_clean_range(__pa(&iram_tlb_phys_addr),
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__pa(&iram_tlb_phys_addr + 1));
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ttbr1 = save_ttbr1();
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/* Now we can change the DDR frequency. */
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if (cpu_is_imx7d())
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imx7d_change_ddr_freq(ddr_rate);
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else if (cpu_is_imx6())
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mx6_change_ddr_freq(ddr_rate, iram_ddr_settings,
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dll_off, iram_iomux_settings);
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restore_ttbr1(ttbr1);
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curr_ddr_rate = ddr_rate;
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#ifdef CONFIG_SMP
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wmb();
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/* DDR frequency change is done . */
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*wait_for_ddr_freq_update = 0;
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dsb();
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/* wake up all the cores. */
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sev();
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#endif
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local_irq_enable();
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printk(KERN_DEBUG "Bus freq set to %d done! cpu=%d\n", ddr_rate, me);
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return 0;
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}
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/* Used by i.MX6SX/i.MX6UL for updating the ddr frequency */
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int update_ddr_freq_imx6_up(int ddr_rate)
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{
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int i;
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bool dll_off = false;
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unsigned long ttbr1;
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int mode = get_bus_freq_mode();
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if (ddr_rate == curr_ddr_rate)
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return 0;
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printk(KERN_DEBUG "\nBus freq set to %d start...\n", ddr_rate);
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if ((mode == BUS_FREQ_LOW) || (mode == BUS_FREQ_AUDIO))
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dll_off = true;
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imx6_busfreq_info->dll_off = dll_off;
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iram_ddr_settings[0][0] = ddr_settings_size;
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iram_iomux_settings[0][0] = iomux_settings_size;
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for (i = 0; i < iram_ddr_settings[0][0]; i++) {
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iram_ddr_settings[i + 1][0] =
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normal_mmdc_settings[i][0];
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iram_ddr_settings[i + 1][1] =
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normal_mmdc_settings[i][1];
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}
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local_irq_disable();
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ttbr1 = save_ttbr1();
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imx6_busfreq_info->freq = ddr_rate;
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imx6_busfreq_info->ddr_settings = iram_ddr_settings;
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imx6_busfreq_info->iomux_offsets = iram_iomux_settings;
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imx6_busfreq_info->mu_delay_val = ((readl_relaxed(mmdc_base + MMDC0_MPMUR0)
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>> MMDC0_MPMUR0_OFFSET) & MMDC0_MPMUR0_MASK);
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imx6_up_change_ddr_freq(imx6_busfreq_info);
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restore_ttbr1(ttbr1);
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curr_ddr_rate = ddr_rate;
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local_irq_enable();
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printk(KERN_DEBUG "Bus freq set to %d done!\n", ddr_rate);
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return 0;
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}
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int init_ddrc_ddr_settings(struct platform_device *busfreq_pdev)
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{
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int ddr_type = imx_ddrc_get_ddr_type();
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#ifdef CONFIG_SMP
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struct device_node *node;
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u32 cpu;
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struct device *dev = &busfreq_pdev->dev;
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int err;
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struct irq_data *d;
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node = of_find_compatible_node(NULL, NULL, "arm,cortex-a7-gic");
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if (!node) {
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printk(KERN_ERR "failed to find imx7d-a7-gic device tree data!\n");
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return -EINVAL;
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}
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gic_dist_base = of_iomap(node, 0);
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WARN(!gic_dist_base, "unable to map gic dist registers\n");
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irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(),
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GFP_KERNEL);
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for_each_online_cpu(cpu) {
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int irq;
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/*
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* set up a reserved interrupt to get all
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* the active cores into a WFE state
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* before changing the DDR frequency.
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*/
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irq = platform_get_irq(busfreq_pdev, cpu);
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err = request_irq(irq, wait_in_wfe_irq,
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IRQF_PERCPU, "ddrc", NULL);
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if (err) {
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dev_err(dev,
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"Busfreq:request_irq failed %d, err = %d\n",
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irq, err);
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return err;
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}
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err = irq_set_affinity(irq, cpumask_of(cpu));
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if (err) {
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dev_err(dev,
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"Busfreq: Cannot set irq affinity irq=%d\n",
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irq);
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return err;
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}
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d = irq_get_irq_data(irq);
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irqs_used[cpu] = d->hwirq + 32;
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}
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/* Store the variable used to communicate between cores */
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wait_for_ddr_freq_update = (u32 *)ddr_freq_change_iram_base;
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imx7_wfe_change_ddr_freq = (void *)fncpy(
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(void *)ddr_freq_change_iram_base + 0x8,
|
|
&imx7_smp_wfe, SMP_WFE_CODE_SIZE - 0x8);
|
|
#endif
|
|
if (ddr_type == IMX_DDR_TYPE_DDR3)
|
|
imx7d_change_ddr_freq = (void *)fncpy(
|
|
(void *)ddr_freq_change_iram_base + SMP_WFE_CODE_SIZE,
|
|
&imx7d_ddr3_freq_change,
|
|
MX7_BUSFREQ_OCRAM_SIZE - SMP_WFE_CODE_SIZE);
|
|
else if (ddr_type == IMX_DDR_TYPE_LPDDR3
|
|
|| ddr_type == IMX_DDR_TYPE_LPDDR2)
|
|
imx7d_change_ddr_freq = (void *)fncpy(
|
|
(void *)ddr_freq_change_iram_base +
|
|
SMP_WFE_CODE_SIZE,
|
|
&imx_lpddr3_freq_change,
|
|
MX7_BUSFREQ_OCRAM_SIZE - SMP_WFE_CODE_SIZE);
|
|
|
|
curr_ddr_rate = ddr_normal_rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Used by i.MX6SX/i.MX6UL for mmdc setting init. */
|
|
int init_mmdc_ddr3_settings_imx6_up(struct platform_device *busfreq_pdev)
|
|
{
|
|
int i;
|
|
struct device_node *node;
|
|
unsigned long ddr_code_size;
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc");
|
|
if (!node) {
|
|
printk(KERN_ERR "failed to find mmdc device tree data!\n");
|
|
return -EINVAL;
|
|
}
|
|
mmdc_base = of_iomap(node, 0);
|
|
WARN(!mmdc_base, "unable to map mmdc registers\n");
|
|
|
|
if (cpu_is_imx6sx())
|
|
node = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-iomuxc");
|
|
else
|
|
node = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-iomuxc");
|
|
if (!node) {
|
|
printk(KERN_ERR "failed to find iomuxc device tree data!\n");
|
|
return -EINVAL;
|
|
}
|
|
iomux_base = of_iomap(node, 0);
|
|
WARN(!iomux_base, "unable to map iomux registers\n");
|
|
|
|
ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6sx) +
|
|
ARRAY_SIZE(ddr3_calibration_mx6sx);
|
|
|
|
normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL);
|
|
memcpy(normal_mmdc_settings, ddr3_dll_mx6sx,
|
|
sizeof(ddr3_dll_mx6sx));
|
|
memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6sx)),
|
|
ddr3_calibration_mx6sx, sizeof(ddr3_calibration_mx6sx));
|
|
|
|
/* store the original DDR settings at boot. */
|
|
for (i = 0; i < ddr_settings_size; i++) {
|
|
/*
|
|
* writes via command mode register cannot be read back.
|
|
* hence hardcode them in the initial static array.
|
|
* this may require modification on a per customer basis.
|
|
*/
|
|
if (normal_mmdc_settings[i][0] != 0x1C)
|
|
normal_mmdc_settings[i][1] =
|
|
readl_relaxed(mmdc_base
|
|
+ normal_mmdc_settings[i][0]);
|
|
}
|
|
|
|
if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz())
|
|
iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6ul);
|
|
else
|
|
iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6sx);
|
|
|
|
ddr_code_size = (&imx6_up_ddr3_freq_change_end -&imx6_up_ddr3_freq_change_start) *4 +
|
|
sizeof(*imx6_busfreq_info);
|
|
imx6_busfreq_info = (struct imx6_busfreq_info *)ddr_freq_change_iram_base;
|
|
|
|
imx6_up_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base + sizeof(*imx6_busfreq_info),
|
|
&imx6_up_ddr3_freq_change, ddr_code_size - sizeof(*imx6_busfreq_info));
|
|
|
|
/*
|
|
* Store the size of the array in iRAM also,
|
|
* increase the size by 8 bytes.
|
|
*/
|
|
iram_iomux_settings = (void *)(ddr_freq_change_iram_base + ddr_code_size);
|
|
iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8;
|
|
|
|
if ((ddr_code_size + (iomux_settings_size + ddr_settings_size) * 8 + 16)
|
|
> ddr_freq_change_total_size) {
|
|
printk(KERN_ERR "Not enough memory allocated for DDR Frequency change code.\n");
|
|
return EINVAL;
|
|
}
|
|
|
|
for (i = 0; i < iomux_settings_size; i++) {
|
|
if (cpu_is_imx6ul() || cpu_is_imx6ull() || cpu_is_imx6ulz()) {
|
|
iomux_offsets_mx6ul[i][1] =
|
|
readl_relaxed(iomux_base +
|
|
iomux_offsets_mx6ul[i][0]);
|
|
iram_iomux_settings[i + 1][0] =
|
|
iomux_offsets_mx6ul[i][0];
|
|
iram_iomux_settings[i + 1][1] =
|
|
iomux_offsets_mx6ul[i][1];
|
|
} else {
|
|
iomux_offsets_mx6sx[i][1] =
|
|
readl_relaxed(iomux_base +
|
|
iomux_offsets_mx6sx[i][0]);
|
|
iram_iomux_settings[i + 1][0] =
|
|
iomux_offsets_mx6sx[i][0];
|
|
iram_iomux_settings[i + 1][1] =
|
|
iomux_offsets_mx6sx[i][1];
|
|
}
|
|
}
|
|
|
|
curr_ddr_rate = ddr_normal_rate;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int init_mmdc_ddr3_settings_imx6_smp(struct platform_device *busfreq_pdev)
|
|
{
|
|
int i;
|
|
struct device_node *node;
|
|
unsigned long ddr_code_size;
|
|
unsigned long wfe_code_size = 0;
|
|
#ifdef CONFIG_SMP
|
|
u32 cpu;
|
|
struct device *dev = &busfreq_pdev->dev;
|
|
int err;
|
|
struct irq_data *d;
|
|
#endif
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-mmdc-combine");
|
|
if (!node) {
|
|
printk(KERN_ERR "failed to find imx6q-mmdc device tree data!\n");
|
|
return -EINVAL;
|
|
}
|
|
mmdc_base = of_iomap(node, 0);
|
|
WARN(!mmdc_base, "unable to map mmdc registers\n");
|
|
|
|
node = NULL;
|
|
if (cpu_is_imx6q())
|
|
node = of_find_compatible_node(NULL, NULL, "fsl,imx6q-iomuxc");
|
|
if (cpu_is_imx6dl())
|
|
node = of_find_compatible_node(NULL, NULL,
|
|
"fsl,imx6dl-iomuxc");
|
|
if (!node) {
|
|
printk(KERN_ERR "failed to find imx6q-iomux device tree data!\n");
|
|
return -EINVAL;
|
|
}
|
|
iomux_base = of_iomap(node, 0);
|
|
WARN(!iomux_base, "unable to map iomux registers\n");
|
|
|
|
node = NULL;
|
|
node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
|
|
if (!node) {
|
|
printk(KERN_ERR "failed to find imx6q-a9-gic device tree data!\n");
|
|
return -EINVAL;
|
|
}
|
|
gic_dist_base = of_iomap(node, 0);
|
|
WARN(!gic_dist_base, "unable to map gic dist registers\n");
|
|
|
|
if (cpu_is_imx6q())
|
|
ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6q) +
|
|
ARRAY_SIZE(ddr3_calibration);
|
|
if (cpu_is_imx6dl())
|
|
ddr_settings_size = ARRAY_SIZE(ddr3_dll_mx6dl) +
|
|
ARRAY_SIZE(ddr3_calibration);
|
|
|
|
normal_mmdc_settings = kmalloc((ddr_settings_size * 8), GFP_KERNEL);
|
|
if (cpu_is_imx6q()) {
|
|
memcpy(normal_mmdc_settings, ddr3_dll_mx6q,
|
|
sizeof(ddr3_dll_mx6q));
|
|
memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6q)),
|
|
ddr3_calibration, sizeof(ddr3_calibration));
|
|
}
|
|
if (cpu_is_imx6dl()) {
|
|
memcpy(normal_mmdc_settings, ddr3_dll_mx6dl,
|
|
sizeof(ddr3_dll_mx6dl));
|
|
memcpy(((char *)normal_mmdc_settings + sizeof(ddr3_dll_mx6dl)),
|
|
ddr3_calibration, sizeof(ddr3_calibration));
|
|
}
|
|
/* store the original DDR settings at boot. */
|
|
for (i = 0; i < ddr_settings_size; i++) {
|
|
/*
|
|
* writes via command mode register cannot be read back.
|
|
* hence hardcode them in the initial static array.
|
|
* this may require modification on a per customer basis.
|
|
*/
|
|
if (normal_mmdc_settings[i][0] != 0x1C)
|
|
normal_mmdc_settings[i][1] =
|
|
readl_relaxed(mmdc_base
|
|
+ normal_mmdc_settings[i][0]);
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
irqs_used = devm_kzalloc(dev, sizeof(u32) * num_present_cpus(),
|
|
GFP_KERNEL);
|
|
|
|
for_each_online_cpu(cpu) {
|
|
int irq;
|
|
|
|
/*
|
|
* set up a reserved interrupt to get all
|
|
* the active cores into a WFE state
|
|
* before changing the DDR frequency.
|
|
*/
|
|
irq = platform_get_irq(busfreq_pdev, cpu);
|
|
err = request_irq(irq, wait_in_wfe_irq,
|
|
IRQF_PERCPU, "mmdc_1", NULL);
|
|
if (err) {
|
|
dev_err(dev,
|
|
"Busfreq:request_irq failed %d, err = %d\n",
|
|
irq, err);
|
|
return err;
|
|
}
|
|
err = irq_set_affinity(irq, cpumask_of(cpu));
|
|
if (err) {
|
|
dev_err(dev,
|
|
"Busfreq: Cannot set irq affinity irq=%d,\n",
|
|
irq);
|
|
return err;
|
|
}
|
|
d = irq_get_irq_data(irq);
|
|
irqs_used[cpu] = d->hwirq + 32;
|
|
}
|
|
#endif
|
|
iomux_settings_size = ARRAY_SIZE(iomux_offsets_mx6q);
|
|
|
|
ddr_code_size = (&mx6_ddr3_freq_change_end -
|
|
&mx6_ddr3_freq_change_start) * 4;
|
|
|
|
mx6_change_ddr_freq = (void *)fncpy((void *)ddr_freq_change_iram_base,
|
|
&mx6_ddr3_freq_change, ddr_code_size);
|
|
|
|
/*
|
|
* Store the size of the array in iRAM also,
|
|
* increase the size by 8 bytes.
|
|
*/
|
|
iram_iomux_settings = (void *)(ddr_freq_change_iram_base +
|
|
ddr_code_size);
|
|
iram_ddr_settings = iram_iomux_settings + (iomux_settings_size * 8) + 8;
|
|
#ifdef CONFIG_SMP
|
|
wfe_freq_change_iram_base = (unsigned long)((u32 *)iram_ddr_settings +
|
|
(ddr_settings_size * 8) + 8);
|
|
|
|
if (wfe_freq_change_iram_base & (FNCPY_ALIGN - 1))
|
|
wfe_freq_change_iram_base += FNCPY_ALIGN -
|
|
((uintptr_t)wfe_freq_change_iram_base % (FNCPY_ALIGN));
|
|
|
|
wfe_code_size = (&wfe_smp_freq_change_end -
|
|
&wfe_smp_freq_change_start) *4;
|
|
|
|
wfe_change_ddr_freq = (void *)fncpy((void *)wfe_freq_change_iram_base,
|
|
&wfe_smp_freq_change, wfe_code_size);
|
|
|
|
/*
|
|
* Store the variable used to communicate
|
|
* between cores in a non-cacheable IRAM area
|
|
*/
|
|
wait_for_ddr_freq_update = (u32 *)&iram_iomux_settings[0][1];
|
|
#endif
|
|
|
|
if ((ddr_code_size + wfe_code_size + (iomux_settings_size +
|
|
ddr_settings_size) * 8 + 16)
|
|
> ddr_freq_change_total_size) {
|
|
printk(KERN_ERR "Not enough memory for DDR Freq scale.\n");
|
|
return EINVAL;
|
|
}
|
|
|
|
if (cpu_is_imx6q()) {
|
|
/* store the IOMUX settings at boot. */
|
|
for (i = 0; i < iomux_settings_size; i++) {
|
|
iomux_offsets_mx6q[i][1] =
|
|
readl_relaxed(iomux_base +
|
|
iomux_offsets_mx6q[i][0]);
|
|
iram_iomux_settings[i + 1][0] =
|
|
iomux_offsets_mx6q[i][0];
|
|
iram_iomux_settings[i + 1][1] =
|
|
iomux_offsets_mx6q[i][1];
|
|
}
|
|
}
|
|
|
|
if (cpu_is_imx6dl()) {
|
|
for (i = 0; i < iomux_settings_size; i++) {
|
|
iomux_offsets_mx6dl[i][1] =
|
|
readl_relaxed(iomux_base +
|
|
iomux_offsets_mx6dl[i][0]);
|
|
iram_iomux_settings[i + 1][0] =
|
|
iomux_offsets_mx6dl[i][0];
|
|
iram_iomux_settings[i + 1][1] =
|
|
iomux_offsets_mx6dl[i][1];
|
|
}
|
|
}
|
|
|
|
curr_ddr_rate = ddr_normal_rate;
|
|
|
|
return 0;
|
|
}
|