391 lines
11 KiB
C
391 lines
11 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/busfreq-imx.h>
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#include <linux/cpuidle.h>
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#include <linux/cpu_pm.h>
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#include <linux/delay.h>
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#include <linux/genalloc.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/psci.h>
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#include <asm/cp15.h>
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#include <asm/cpuidle.h>
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#include <asm/fncpy.h>
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#include <asm/mach/map.h>
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#include <asm/proc-fns.h>
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#include <asm/suspend.h>
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#include <asm/tlb.h>
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#include <uapi/linux/psci.h>
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#include "common.h"
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#include "cpuidle.h"
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#include "hardware.h"
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#define XTALOSC24M_OSC_CONFIG0 0x10
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#define XTALOSC24M_OSC_CONFIG1 0x20
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#define XTALOSC24M_OSC_CONFIG2 0x30
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#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT 24
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#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK 0xf
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#define XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT 16
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#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK 0xf
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#define XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT 12
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#define XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT 4
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#define XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT 1
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#define XTALOSC24M_OSC_CONFIG0_START_SHIFT 0
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#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT 20
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#define XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT 0
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#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK 0xfff
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#define XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT 0
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#define XTALOSC_CTRL_24M 0x0
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#define XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT 13
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#define REG_SET 0x4
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static void __iomem *wfi_iram_base;
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static void __iomem *wfi_iram_base_phys;
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extern unsigned long iram_tlb_phys_addr;
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struct imx7_pm_base {
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phys_addr_t pbase;
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void __iomem *vbase;
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};
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struct imx7_cpuidle_pm_info {
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phys_addr_t vbase; /* The virtual address of pm_info. */
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phys_addr_t pbase; /* The physical address of pm_info. */
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phys_addr_t resume_addr; /* The physical resume address for asm code */
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u32 pm_info_size;
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u32 ttbr;
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u32 num_online_cpus;
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u32 num_lpi_cpus;
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atomic_t val;
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atomic_t flag0;
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atomic_t flag1;
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struct imx7_pm_base ddrc_base;
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struct imx7_pm_base ccm_base;
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struct imx7_pm_base anatop_base;
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struct imx7_pm_base src_base;
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struct imx7_pm_base iomuxc_gpr_base;
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struct imx7_pm_base gpc_base;
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struct imx7_pm_base gic_dist_base;
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} __aligned(8);
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static atomic_t master_lpi = ATOMIC_INIT(0);
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static atomic_t master_wait = ATOMIC_INIT(0);
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static void (*imx7d_wfi_in_iram_fn)(void __iomem *iram_vbase);
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static struct imx7_cpuidle_pm_info *cpuidle_pm_info;
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#define MX7D_POWERDWN_IDLE_PARAM \
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((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \
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(1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \
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(PSCI_POWER_STATE_TYPE_POWER_DOWN << PSCI_0_2_POWER_STATE_TYPE_SHIFT))
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#define MX7D_STANDBY_IDLE_PARAM \
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((1 << PSCI_0_2_POWER_STATE_ID_SHIFT) | \
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(1 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) | \
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(PSCI_POWER_STATE_TYPE_STANDBY << PSCI_0_2_POWER_STATE_TYPE_SHIFT))
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/* Mapped for the kernel, unlike cpuidle_pm_info->gic_dist_base.vbase */
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static void __iomem *imx7d_cpuidle_gic_base;
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static void imx_pen_lock(int cpu)
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{
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if (cpu == 0) {
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atomic_set(&cpuidle_pm_info->flag0, 1);
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dsb();
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atomic_set(&cpuidle_pm_info->val, cpu);
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do {
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dsb();
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} while (atomic_read(&cpuidle_pm_info->flag1) == 1
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&& atomic_read(&cpuidle_pm_info->val) == cpu)
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;
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} else {
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atomic_set(&cpuidle_pm_info->flag1, 1);
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dsb();
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atomic_set(&cpuidle_pm_info->val, cpu);
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do {
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dsb();
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} while (atomic_read(&cpuidle_pm_info->flag0) == 1
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&& atomic_read(&cpuidle_pm_info->val) == cpu)
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;
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}
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}
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static void imx_pen_unlock(int cpu)
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{
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dsb();
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if (cpu == 0)
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atomic_set(&cpuidle_pm_info->flag0, 0);
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else
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atomic_set(&cpuidle_pm_info->flag1, 0);
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}
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static int imx7d_idle_finish(unsigned long val)
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{
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if (psci_ops.cpu_suspend)
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psci_ops.cpu_suspend(MX7D_POWERDWN_IDLE_PARAM, __pa(cpu_resume));
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else
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imx7d_wfi_in_iram_fn(wfi_iram_base);
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return 0;
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}
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static bool imx7d_gic_sgis_pending(void)
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{
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void __iomem *sgip_base = imx7d_cpuidle_gic_base + 0x1f20;
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return (readl_relaxed(sgip_base + 0x0) |
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readl_relaxed(sgip_base + 0x4) |
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readl_relaxed(sgip_base + 0x8) |
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readl_relaxed(sgip_base + 0xc));
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}
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static DEFINE_SPINLOCK(psci_lock);
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static int imx7d_enter_low_power_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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int mode = get_bus_freq_mode();
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if ((index == 1) || ((mode != BUS_FREQ_LOW) && index == 2)) {
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index = 1;
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if (atomic_inc_return(&master_wait) == num_online_cpus())
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imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED);
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cpu_do_idle();
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atomic_dec(&master_wait);
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imx_gpcv2_set_lpm_mode(WAIT_CLOCKED);
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} else {
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if (psci_ops.cpu_suspend) {
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cpu_pm_enter();
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spin_lock(&psci_lock);
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if (atomic_inc_return(&master_lpi) == num_online_cpus()) {
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if (imx7d_gic_sgis_pending()) {
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atomic_dec(&master_lpi);
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index = -1;
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goto psci_skip_lpi_flow;
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}
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imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED);
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imx_gpcv2_set_cpu_power_gate_in_idle(true);
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cpu_cluster_pm_enter();
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}
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spin_unlock(&psci_lock);
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cpu_suspend(0, imx7d_idle_finish);
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spin_lock(&psci_lock);
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if (atomic_read(&master_lpi) == num_online_cpus()) {
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cpu_cluster_pm_exit();
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imx_gpcv2_set_cpu_power_gate_in_idle(false);
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imx_gpcv2_set_lpm_mode(WAIT_CLOCKED);
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}
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atomic_dec(&master_lpi);
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psci_skip_lpi_flow:
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spin_unlock(&psci_lock);
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cpu_pm_exit();
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} else {
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imx_pen_lock(dev->cpu);
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cpuidle_pm_info->num_online_cpus = num_online_cpus();
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++cpuidle_pm_info->num_lpi_cpus;
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cpu_pm_enter();
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if (cpuidle_pm_info->num_lpi_cpus ==
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cpuidle_pm_info->num_online_cpus) {
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/*
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* GPC will not wake on SGIs so check for them
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* manually here. At this point we know the other cpu
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* is in wfi or waiting for the lock and can't send
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* any additional IPIs.
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*/
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if (imx7d_gic_sgis_pending()) {
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index = -1;
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goto skip_lpi_flow;
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}
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imx_gpcv2_set_lpm_mode(WAIT_UNCLOCKED);
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imx_gpcv2_set_cpu_power_gate_in_idle(true);
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cpu_cluster_pm_enter();
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} else {
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imx_set_cpu_jump(dev->cpu, ca7_cpu_resume);
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}
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cpu_suspend(0, imx7d_idle_finish);
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if (cpuidle_pm_info->num_lpi_cpus ==
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cpuidle_pm_info->num_online_cpus) {
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cpu_cluster_pm_exit();
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imx_gpcv2_set_cpu_power_gate_in_idle(false);
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imx_gpcv2_set_lpm_mode(WAIT_CLOCKED);
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}
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skip_lpi_flow:
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cpu_pm_exit();
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--cpuidle_pm_info->num_lpi_cpus;
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imx_pen_unlock(dev->cpu);
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}
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}
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return index;
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}
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static struct cpuidle_driver imx7d_cpuidle_driver = {
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.name = "imx7d_cpuidle",
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.owner = THIS_MODULE,
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.states = {
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/* WFI */
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ARM_CPUIDLE_WFI_STATE,
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/* WAIT MODE */
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{
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.exit_latency = 50,
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.target_residency = 75,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.enter = imx7d_enter_low_power_idle,
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.name = "WAIT",
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.desc = "Clock off",
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},
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/* LOW POWER IDLE */
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{
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.exit_latency = 10000,
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.target_residency = 20000,
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.flags = CPUIDLE_FLAG_TIMER_STOP,
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.enter = imx7d_enter_low_power_idle,
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.name = "LOW-POWER-IDLE",
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.desc = "ARM power off",
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},
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},
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.state_count = 3,
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.safe_state_index = 0,
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};
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int imx7d_enable_rcosc(void)
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{
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void __iomem *anatop_base =
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(void __iomem *)IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR);
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u32 val;
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imx_gpcv2_set_lpm_mode(WAIT_CLOCKED);
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/* set RC-OSC freq and turn it on */
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writel_relaxed(0x1 << XTALOSC_CTRL_24M_RC_OSC_EN_SHIFT,
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anatop_base + XTALOSC_CTRL_24M + REG_SET);
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/*
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* config RC-OSC freq
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* tune_enable = 1;tune_start = 1;hyst_plus = 0;hyst_minus = 0;
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* osc_prog = 0xa7;
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*/
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writel_relaxed(
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0x4 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_CUR_SHIFT |
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0xa7 << XTALOSC24M_OSC_CONFIG0_RC_OSC_PROG_SHIFT |
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0x1 << XTALOSC24M_OSC_CONFIG0_ENABLE_SHIFT |
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0x1 << XTALOSC24M_OSC_CONFIG0_START_SHIFT,
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anatop_base + XTALOSC24M_OSC_CONFIG0);
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/* set count_trg = 0x2dc */
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writel_relaxed(
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0x40 << XTALOSC24M_OSC_CONFIG1_COUNT_RC_CUR_SHIFT |
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0x2dc << XTALOSC24M_OSC_CONFIG1_COUNT_RC_TRG_SHIFT,
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anatop_base + XTALOSC24M_OSC_CONFIG1);
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/* wait at least 4ms according to hardware design */
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mdelay(6);
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/*
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* now add some hysteresis, hyst_plus=3, hyst_minus=3
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* (the minimum hysteresis that looks good is 2)
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*/
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val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG0);
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val &= ~((XTALOSC24M_OSC_CONFIG0_HYST_MINUS_MASK <<
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XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) |
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(XTALOSC24M_OSC_CONFIG0_HYST_PLUS_MASK <<
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XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT));
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val |= (0x3 << XTALOSC24M_OSC_CONFIG0_HYST_MINUS_SHIFT) |
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(0x3 << XTALOSC24M_OSC_CONFIG0_HYST_PLUS_SHIFT);
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writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG0);
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/* set the count_1m_trg = 0x2d7 */
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val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG2);
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val &= ~(XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_MASK <<
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XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT);
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val |= 0x2d7 << XTALOSC24M_OSC_CONFIG2_COUNT_1M_TRG_SHIFT;
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writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG2);
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/*
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* hardware design require to write XTALOSC24M_OSC_CONFIG0 or
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* XTALOSC24M_OSC_CONFIG1 to
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* make XTALOSC24M_OSC_CONFIG2 write work
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*/
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val = readl_relaxed(anatop_base + XTALOSC24M_OSC_CONFIG1);
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writel_relaxed(val, anatop_base + XTALOSC24M_OSC_CONFIG1);
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return 0;
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}
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int __init imx7d_cpuidle_init(void)
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{
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wfi_iram_base_phys = (void *)(iram_tlb_phys_addr +
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MX7_CPUIDLE_OCRAM_ADDR_OFFSET);
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/* Make sure wfi_iram_base is 8 byte aligned. */
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if ((uintptr_t)(wfi_iram_base_phys) & (FNCPY_ALIGN - 1))
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wfi_iram_base_phys += FNCPY_ALIGN -
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((uintptr_t)wfi_iram_base_phys % (FNCPY_ALIGN));
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wfi_iram_base = (void *)IMX_IO_P2V((unsigned long) wfi_iram_base_phys);
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cpuidle_pm_info = wfi_iram_base;
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cpuidle_pm_info->vbase = (phys_addr_t) wfi_iram_base;
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cpuidle_pm_info->pbase = (phys_addr_t) wfi_iram_base_phys;
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cpuidle_pm_info->pm_info_size = sizeof(*cpuidle_pm_info);
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cpuidle_pm_info->resume_addr = virt_to_phys(ca7_cpu_resume);
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cpuidle_pm_info->num_online_cpus = num_online_cpus();
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cpuidle_pm_info->ddrc_base.pbase = MX7D_DDRC_BASE_ADDR;
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cpuidle_pm_info->ddrc_base.vbase =
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(void __iomem *)IMX_IO_P2V(MX7D_DDRC_BASE_ADDR);
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cpuidle_pm_info->ccm_base.pbase = MX7D_CCM_BASE_ADDR;
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cpuidle_pm_info->ccm_base.vbase =
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(void __iomem *)IMX_IO_P2V(MX7D_CCM_BASE_ADDR);
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cpuidle_pm_info->anatop_base.pbase = MX7D_ANATOP_BASE_ADDR;
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cpuidle_pm_info->anatop_base.vbase =
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(void __iomem *)IMX_IO_P2V(MX7D_ANATOP_BASE_ADDR);
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cpuidle_pm_info->src_base.pbase = MX7D_SRC_BASE_ADDR;
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cpuidle_pm_info->src_base.vbase =
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(void __iomem *)IMX_IO_P2V(MX7D_SRC_BASE_ADDR);
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cpuidle_pm_info->iomuxc_gpr_base.pbase = MX7D_IOMUXC_GPR_BASE_ADDR;
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cpuidle_pm_info->iomuxc_gpr_base.vbase =
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(void __iomem *)IMX_IO_P2V(MX7D_IOMUXC_GPR_BASE_ADDR);
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cpuidle_pm_info->gpc_base.pbase = MX7D_GPC_BASE_ADDR;
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cpuidle_pm_info->gpc_base.vbase =
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(void __iomem *)IMX_IO_P2V(MX7D_GPC_BASE_ADDR);
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cpuidle_pm_info->gic_dist_base.pbase = MX7D_GIC_BASE_ADDR;
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cpuidle_pm_info->gic_dist_base.vbase =
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(void __iomem *)IMX_IO_P2V(MX7D_GIC_BASE_ADDR);
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imx7d_cpuidle_gic_base = ioremap(MX7D_GIC_BASE_ADDR, MX7D_GIC_SIZE);
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imx7d_enable_rcosc();
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/* code size should include cpuidle_pm_info size */
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if (!psci_ops.cpu_suspend) {
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imx7d_wfi_in_iram_fn = (void *)fncpy(wfi_iram_base +
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sizeof(*cpuidle_pm_info),
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&imx7d_low_power_idle,
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MX7_CPUIDLE_OCRAM_SIZE - sizeof(*cpuidle_pm_info));
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}
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return cpuidle_register(&imx7d_cpuidle_driver, NULL);
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}
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