619 lines
12 KiB
ArmAsm
619 lines
12 KiB
ArmAsm
/*
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* Copyright (C) 2012-2016 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include "hardware.h"
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#define PL310_AUX_CTRL 0x104
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#define PL310_DCACHE_LOCKDOWN_BASE 0x900
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#define PL310_AUX_16WAY_BIT 0x10000
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#define PL310_LOCKDOWN_NBREGS 8
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#define PL310_LOCKDOWN_SZREG 4
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#define PL310_8WAYS_MASK 0x00FF
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#define PL310_16WAYS_UPPERMASK 0xFF00
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.globl imx6_lpddr2_freq_change_start
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.globl imx6_lpddr2_freq_change_end
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.macro mx6sl_switch_to_24MHz
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/*
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* Set MMDC clock to be sourced from PLL3.
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* Ensure first periph2_clk2 is sourced from PLL3.
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* Set the PERIPH2_CLK2_PODF to divide by 2.
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*/
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ldr r6, [r2, #0x14]
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bic r6, r6, #0x7
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orr r6, r6, #0x1
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str r6, [r2, #0x14]
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/* Select PLL3 to source MMDC. */
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ldr r6, [r2, #0x18]
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bic r6, r6, #0x100000
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str r6, [r2, #0x18]
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/* Swtich periph2_clk_sel to run from PLL3. */
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ldr r6, [r2, #0x14]
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orr r6, r6, #0x4000000
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str r6, [r2, #0x14]
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periph2_clk_switch1:
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ldr r6, [r2, #0x48]
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cmp r6, #0
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bne periph2_clk_switch1
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/*
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* Need to clock gate the 528 PFDs before
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* powering down PLL2.
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* Only the PLL2_PFD2_400M should be ON
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* at this time, so only clock gate that one.
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*/
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ldr r6, [r3, #0x100]
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orr r6, r6, #0x800000
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str r6, [r3, #0x100]
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/*
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* Set PLL2 to bypass state. We should be here
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* only if MMDC is not sourced from PLL2.
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*/
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ldr r6, [r3, #0x30]
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orr r6, r6, #0x10000
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str r6, [r3, #0x30]
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ldr r6, [r3, #0x30]
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orr r6, r6, #0x1000
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str r6, [r3, #0x30]
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/* Ensure pre_periph2_clk_mux is set to pll2 */
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ldr r6, [r2, #0x18]
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bic r6, r6, #0x600000
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str r6, [r2, #0x18]
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/* Set MMDC clock to be sourced from the bypassed PLL2. */
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ldr r6, [r2, #0x14]
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bic r6, r6, #0x4000000
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str r6, [r2, #0x14]
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periph2_clk_switch2:
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ldr r6, [r2, #0x48]
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cmp r6, #0
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bne periph2_clk_switch2
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/*
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* Now move MMDC back to periph2_clk2 source.
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* after selecting PLL2 as the option.
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* Select PLL2 as the source.
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*/
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ldr r6, [r2, #0x18]
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orr r6, r6, #0x100000
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str r6, [r2, #0x18]
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/* set periph2_clk2_podf to divide by 1. */
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ldr r6, [r2, #0x14]
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bic r6, r6, #0x7
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str r6, [r2, #0x14]
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/* Now move periph2_clk to periph2_clk2 source */
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ldr r6, [r2, #0x14]
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orr r6, r6, #0x4000000
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str r6, [r2, #0x14]
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periph2_clk_switch3:
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ldr r6, [r2, #0x48]
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cmp r6, #0
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bne periph2_clk_switch3
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/* Now set the MMDC PODF back to 1.*/
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ldr r6, [r2, #0x14]
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bic r6, r6, #0x38
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str r6, [r2, #0x14]
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mmdc_podf0:
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ldr r6, [r2, #0x48]
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cmp r6, #0
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bne mmdc_podf0
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.endm
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.macro ddr_switch_400MHz
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/* Set MMDC divider first, in case PLL3 is at 480MHz. */
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ldr r6, [r3, #0x10]
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and r6, r6, #0x10000
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cmp r6, #0x10000
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beq pll3_in_bypass
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/* Set MMDC divder to divide by 2. */
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ldr r6, [r2, #0x14]
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bic r6, r6, #0x38
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orr r6, r6, #0x8
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str r6, [r2, #0x14]
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mmdc_podf:
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ldr r6, [r2, #0x48]
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cmp r6, #0
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bne mmdc_podf
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pll3_in_bypass:
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/*
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* Check if we are switching between
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* 400Mhz <-> 100MHz.If so, we should
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* try to source MMDC from PLL2_200M.
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*/
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cmp r1, #0
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beq not_low_bus_freq
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/* Ensure that MMDC is sourced from PLL2 mux first. */
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ldr r6, [r2, #0x14]
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bic r6, r6, #0x4000000
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str r6, [r2, #0x14]
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periph2_clk_switch4:
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ldr r6, [r2, #0x48]
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cmp r6, #0
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bne periph2_clk_switch4
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not_low_bus_freq:
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/* Now ensure periph2_clk2_sel mux is set to PLL3 */
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ldr r6, [r2, #0x18]
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bic r6, r6, #0x100000
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str r6, [r2, #0x18]
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/* Now switch MMDC to PLL3. */
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ldr r6, [r2, #0x14]
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orr r6, r6, #0x4000000
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str r6, [r2, #0x14]
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periph2_clk_switch5:
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ldr r6, [r2, #0x48]
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cmp r6, #0
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bne periph2_clk_switch5
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/*
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* Check if PLL2 is already unlocked.
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* If so do nothing with PLL2.
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*/
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cmp r1, #0
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beq pll2_already_on
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/* Now power up PLL2 and unbypass it. */
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ldr r6, [r3, #0x30]
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bic r6, r6, #0x1000
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str r6, [r3, #0x30]
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/* Make sure PLL2 has locked.*/
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wait_for_pll_lock:
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ldr r6, [r3, #0x30]
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and r6, r6, #0x80000000
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cmp r6, #0x80000000
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bne wait_for_pll_lock
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ldr r6, [r3, #0x30]
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bic r6, r6, #0x10000
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str r6, [r3, #0x30]
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/*
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* Need to enable the 528 PFDs after
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* powering up PLL2.
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* Only the PLL2_PFD2_400M should be ON
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* as it feeds the MMDC. Rest should have
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* been managed by clock code.
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*/
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ldr r6, [r3, #0x100]
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bic r6, r6, #0x800000
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str r6, [r3, #0x100]
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pll2_already_on:
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/*
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* Now switch MMDC clk back to pll2_mux option.
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* Ensure pre_periph2_clk2 is set to pll2_pfd_400M.
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* If switching to audio DDR freq, set the
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* pre_periph2_clk2 to PLL2_PFD_200M
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*/
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ldr r6, =400000000
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cmp r6, r0
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bne use_pll2_pfd_200M
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ldr r6, [r2, #0x18]
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bic r6, r6, #0x600000
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orr r6, r6, #0x200000
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str r6, [r2, #0x18]
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ldr r6, =400000000
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b cont2
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use_pll2_pfd_200M:
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ldr r6, [r2, #0x18]
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orr r6, r6, #0x600000
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str r6, [r2, #0x18]
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ldr r6, =200000000
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cont2:
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ldr r4, [r2, #0x14]
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bic r4, r4, #0x4000000
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str r4, [r2, #0x14]
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periph2_clk_switch6:
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ldr r4, [r2, #0x48]
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cmp r4, #0
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bne periph2_clk_switch6
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change_divider_only:
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/*
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* Calculate the MMDC divider
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* based on the requested freq.
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*/
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ldr r4, =0
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Loop2:
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sub r6, r6, r0
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cmp r6, r0
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blt Div_Found
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add r4, r4, #1
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bgt Loop2
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/* Shift divider into correct offset. */
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lsl r4, r4, #3
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Div_Found:
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/* Set the MMDC PODF. */
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ldr r6, [r2, #0x14]
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bic r6, r6, #0x38
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orr r6, r6, r4
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str r6, [r2, #0x14]
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mmdc_podf1:
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ldr r6, [r2, #0x48]
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cmp r6, #0
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bne mmdc_podf1
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.endm
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.macro mmdc_clk_lower_100MHz
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/*
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* Prior to reducing the DDR frequency (at 528/400 MHz),
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* read the Measure unit count bits (MU_UNIT_DEL_NUM)
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*/
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ldr r5, =0x8B8
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ldr r6, [r8, r5]
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/* Original MU unit count */
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mov r6, r6, LSR #16
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ldr r4, =0x3FF
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and r6, r6, r4
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/* Original MU unit count * 2 */
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mov r7, r6, LSL #1
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/*
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* Bypass the automatic measure unit when below 100 MHz
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* by setting the Measure unit bypass enable bit (MU_BYP_EN)
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*/
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ldr r6, [r8, r5]
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orr r6, r6, #0x400
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str r6, [r8, r5]
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/*
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* Double the measure count value read in step 1 and program it in the
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* measurement bypass bits (MU_BYP_VAL) of the MMDC PHY Measure Unit
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* Register for the reduced frequency operation below 100 MHz
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*/
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ldr r6, [r8, r5]
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ldr r4, =0x3FF
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bic r6, r6, r4
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orr r6, r6, r7
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str r6, [r8, r5]
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.endm
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.macro mmdc_clk_above_100MHz
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/* Make sure that the PHY measurement unit is NOT in bypass mode */
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ldr r5, =0x8B8
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ldr r6, [r8, r5]
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bic r6, r6, #0x400
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str r6, [r8, r5]
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/* Now perform a Force Measurement. */
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ldr r6, [r8, r5]
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orr r6, r6, #0x800
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str r6, [r8, r5]
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/* Wait for FRC_MSR to clear. */
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force_measure1:
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ldr r6, [r8, r5]
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and r6, r6, #0x800
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cmp r6, #0x0
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bne force_measure1
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.endm
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/*
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* mx6_lpddr2_freq_change
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*
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* Make sure DDR is in self-refresh.
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* IRQs are already disabled.
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* r0 : DDR freq.
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* r1: low_bus_freq_mode flag
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*/
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.align 3
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ENTRY(mx6_lpddr2_freq_change)
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imx6_lpddr2_freq_change_start:
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push {r4-r10}
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/*
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* To ensure no page table walks occur in DDR, we
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* have a another page table stored in IRAM that only
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* contains entries pointing to IRAM, AIPS1 and AIPS2.
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* We need to set the TTBR1 to the new IRAM TLB.
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* Do the following steps:
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* 1. Flush the Branch Target Address Cache (BTAC)
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* 2. Set TTBR1 to point to IRAM page table.
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* 3. Disable page table walks in TTBR0 (PD0 = 1)
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* 4. Set TTBR0.N=1, implying 0-2G is translated by TTBR0
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* and 2-4G is translated by TTBR1.
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*/
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ldr r6, =iram_tlb_phys_addr
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ldr r7, [r6]
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/* Disable Branch Prediction, Z bit in SCTLR. */
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mrc p15, 0, r6, c1, c0, 0
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bic r6, r6, #0x800
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mcr p15, 0, r6, c1, c0, 0
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/* Flush the Branch Target Address Cache (BTAC) */
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ldr r6, =0x0
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mcr p15, 0, r6, c7, c1, 6
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dsb
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isb
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/* Store the IRAM table in TTBR1 */
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mcr p15, 0, r7, c2, c0, 1
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/* Read TTBCR and set PD0=1, N = 1 */
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mrc p15, 0, r6, c2, c0, 2
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orr r6, r6, #0x11
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mcr p15, 0, r6, c2, c0, 2
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dsb
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isb
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/* flush the TLB */
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ldr r6, =0x0
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mcr p15, 0, r6, c8, c3, 0
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/* Disable L1 data cache. */
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mrc p15, 0, r6, c1, c0, 0
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bic r6, r6, #0x4
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mcr p15, 0, r6, c1, c0, 0
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dsb
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isb
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#ifdef CONFIG_CACHE_L2X0
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/*
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* Need to make sure the buffers in L2 are drained.
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* Performing a sync operation does this.
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*/
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ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
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/* Wait for background operations to complete. */
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wait_for_l2_to_idle:
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ldr r6, [r7, #0x730]
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cmp r6, #0x0
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bne wait_for_l2_to_idle
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mov r6, #0x0
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str r6, [r7, #0x730]
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/*
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* The second dsb might be needed to keep cache sync (device write)
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* ordering with the memory accesses before it.
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*/
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dsb
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isb
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ldr r3, [r7, #PL310_AUX_CTRL]
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tst r3, #PL310_AUX_16WAY_BIT
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mov r3, #PL310_8WAYS_MASK
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orrne r3, #PL310_16WAYS_UPPERMASK
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mov r6, #PL310_LOCKDOWN_NBREGS
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add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE
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1: /* lock Dcache and Icache */
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str r3, [r5], #PL310_LOCKDOWN_SZREG
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str r3, [r5], #PL310_LOCKDOWN_SZREG
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subs r6, r6, #1
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bne 1b
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#endif
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ldr r3, =IMX_IO_P2V(MX6Q_ANATOP_BASE_ADDR)
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ldr r2, =IMX_IO_P2V(MX6Q_CCM_BASE_ADDR)
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ldr r8, =IMX_IO_P2V(MX6Q_MMDC_P0_BASE_ADDR)
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/* Disable Automatic power savings. */
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ldr r6, [r8, #0x404]
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orr r6, r6, #0x01
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str r6, [r8, #0x404]
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/* MMDC0_MDPDC disable power down timer */
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ldr r6, [r8, #0x4]
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bic r6, r6, #0xff00
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str r6, [r8, #0x4]
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/* Delay for a while */
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ldr r10, =10
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delay1:
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ldr r7, =0
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cont1:
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ldr r6, [r8, r7]
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add r7, r7, #4
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cmp r7, #16
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bne cont1
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sub r10, r10, #1
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cmp r10, #0
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bgt delay1
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/* Make the DDR explicitly enter self-refresh. */
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ldr r6, [r8, #0x404]
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orr r6, r6, #0x200000
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str r6, [r8, #0x404]
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poll_dvfs_set_1:
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ldr r6, [r8, #0x404]
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and r6, r6, #0x2000000
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cmp r6, #0x2000000
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bne poll_dvfs_set_1
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/* set SBS step-by-step mode */
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ldr r6, [r8, #0x410]
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orr r6, r6, #0x100
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str r6, [r8, #0x410]
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ldr r10, =100000000
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cmp r0, r10
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bgt set_ddr_mu_above_100
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mmdc_clk_lower_100MHz
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set_ddr_mu_above_100:
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ldr r10, =24000000
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cmp r0, r10
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beq set_to_24MHz
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ddr_switch_400MHz
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ldr r10,=100000000
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cmp r0, r10
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blt done
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mmdc_clk_above_100MHz
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b done
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set_to_24MHz:
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mx6sl_switch_to_24MHz
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done:
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/* clear DVFS - exit from self refresh mode */
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ldr r6, [r8, #0x404]
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bic r6, r6, #0x200000
|
|
str r6, [r8, #0x404]
|
|
|
|
poll_dvfs_clear_1:
|
|
ldr r6, [r8, #0x404]
|
|
and r6, r6, #0x2000000
|
|
cmp r6, #0x2000000
|
|
beq poll_dvfs_clear_1
|
|
|
|
/* Enable Automatic power savings. */
|
|
ldr r6, [r8, #0x404]
|
|
bic r6, r6, #0x01
|
|
str r6, [r8, #0x404]
|
|
|
|
ldr r10, =24000000
|
|
cmp r0, r10
|
|
beq skip_power_down
|
|
|
|
/* Enable MMDC power down timer. */
|
|
ldr r6, [r8, #0x4]
|
|
orr r6, r6, #0x5500
|
|
str r6, [r8, #0x4]
|
|
|
|
skip_power_down:
|
|
/* clear SBS - unblock DDR accesses */
|
|
ldr r6, [r8, #0x410]
|
|
bic r6, r6, #0x100
|
|
str r6, [r8, #0x410]
|
|
|
|
#ifdef CONFIG_CACHE_L2X0
|
|
ldr r7, =IMX_IO_P2V(MX6Q_L2_BASE_ADDR)
|
|
ldr r3, [r7, #PL310_AUX_CTRL]
|
|
tst r3, #PL310_AUX_16WAY_BIT
|
|
mov r6, #PL310_LOCKDOWN_NBREGS
|
|
mov r3, #0x00 /* 8 ways mask */
|
|
orrne r3, #0x0000 /* 16 ways mask */
|
|
add r5, r7, #PL310_DCACHE_LOCKDOWN_BASE
|
|
1: /* lock Dcache and Icache */
|
|
str r3, [r5], #PL310_LOCKDOWN_SZREG
|
|
str r3, [r5], #PL310_LOCKDOWN_SZREG
|
|
subs r6, r6, #1
|
|
bne 1b
|
|
#endif
|
|
|
|
/* Enable L1 data cache. */
|
|
mrc p15, 0, r6, c1, c0, 0
|
|
orr r6, r6, #0x4
|
|
mcr p15, 0, r6, c1, c0, 0
|
|
|
|
/* Restore the TTBCR */
|
|
dsb
|
|
isb
|
|
|
|
/* Read TTBCR and set PD0=0, N = 0 */
|
|
mrc p15, 0, r6, c2, c0, 2
|
|
bic r6, r6, #0x11
|
|
mcr p15, 0, r6, c2, c0, 2
|
|
dsb
|
|
isb
|
|
|
|
/* flush the TLB */
|
|
ldr r6, =0x0
|
|
mcr p15, 0, r6, c8, c3, 0
|
|
|
|
dsb
|
|
isb
|
|
|
|
/* Enable Branch Prediction, Z bit in SCTLR. */
|
|
mrc p15, 0, r6, c1, c0, 0
|
|
orr r6, r6, #0x800
|
|
mcr p15, 0, r6, c1, c0, 0
|
|
|
|
/* Flush the Branch Target Address Cache (BTAC) */
|
|
ldr r6, =0x0
|
|
mcr p15, 0, r6, c7, c1, 6
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
nop
|
|
|
|
pop {r4-r10}
|
|
|
|
/* Restore registers */
|
|
mov pc, lr
|
|
|
|
/*
|
|
* Add ltorg here to ensure that all
|
|
* literals are stored here and are
|
|
* within the text space.
|
|
*/
|
|
.ltorg
|
|
imx6_lpddr2_freq_change_end:
|