Paul Cercueil ca4fd0284c clk: ingenic: Fix divider calculation with div tables ... commit 11a163f2c7 upstream. The previous code assumed that a higher hardware value always resulted in a bigger divider, which is correct for the regular clocks, but is an invalid assumption when a divider table is provided for the clock. Perfect example of this is the PLL0_HALF clock, which applies a /2 divider with the hardware value 0, and a /1 divider otherwise. Fixes: a9fa2893fc ("clk: ingenic: Add support for divider tables") Cc: <stable@vger.kernel.org> # 5.2 Signed-off-by: Paul Cercueil <paul@crapouillou.net> Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net Signed-off-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>		2020-12-30 11:51:45 +01:00
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Kconfig	clk: ingenic: Add driver for the TCU clocks	2019-08-08 15:30:07 -07:00
Makefile	clk: ingenic: Add driver for the TCU clocks	2019-08-08 15:30:07 -07:00
cgu.c	clk: ingenic: Fix divider calculation with div tables	2020-12-30 11:51:45 +01:00
cgu.h	This round of clk driver and framework updates is heavy on the driver update	2019-07-17 10:07:48 -07:00
jz4725b-cgu.c	clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro	2019-08-12 10:59:50 -07:00
jz4740-cgu.c	Main MIPS changes for v5.4:	2019-09-22 09:30:30 -07:00
jz4770-cgu.c	clk: ingenic/jz4770: Exit with error if CGU init failed	2020-04-17 10:50:21 +02:00
jz4780-cgu.c	clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro	2019-08-12 10:59:50 -07:00
pm.c	clk: ingenic: Handle setting the Low-Power Mode bit	2019-06-25 15:43:15 -07:00
pm.h	clk: ingenic: Handle setting the Low-Power Mode bit	2019-06-25 15:43:15 -07:00
tcu.c	clk: ingenic/TCU: Fix round_rate returning error	2020-04-17 10:50:21 +02:00