570 lines
15 KiB
C
570 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include <dt-bindings/firmware/imx/rsrc.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/firmware/imx/sci.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/phy/phy-mixel-lvds.h>
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#include <drm/bridge/fsl_imx_ldb.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_probe_helper.h>
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#include "imx-drm.h"
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#define DRIVER_NAME "imx8qm-ldb"
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#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
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#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
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#define LDB_CH0_MODE_EN_MASK (3 << 0)
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#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
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#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
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#define LDB_CH1_MODE_EN_MASK (3 << 2)
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#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
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#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
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#define LDB_CH0_10BIT_EN (1 << 22)
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#define LDB_CH1_10BIT_EN (1 << 23)
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#define LDB_CH0_DATA_WIDTH_24BIT (1 << 24)
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#define LDB_CH1_DATA_WIDTH_24BIT (1 << 26)
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#define LDB_CH0_DATA_WIDTH_30BIT (2 << 24)
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#define LDB_CH1_DATA_WIDTH_30BIT (2 << 26)
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struct imx8qm_ldb;
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struct imx8qm_ldb_channel {
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struct ldb_channel base;
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struct imx8qm_ldb *imx8qm_ldb;
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struct drm_connector connector;
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struct drm_encoder encoder;
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struct phy *phy;
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bool phy_is_on;
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u32 bus_flags;
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};
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static inline struct imx8qm_ldb_channel *
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con_to_imx8qm_ldb_ch(struct drm_connector *c)
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{
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return container_of(c, struct imx8qm_ldb_channel, connector);
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}
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static inline struct imx8qm_ldb_channel *
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enc_to_imx8qm_ldb_ch(struct drm_encoder *e)
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{
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return container_of(e, struct imx8qm_ldb_channel, encoder);
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}
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struct imx8qm_ldb {
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struct ldb base;
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struct imx8qm_ldb_channel channel[LDB_CH_NUM];
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struct clk *clk_pixel;
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struct clk *clk_bypass;
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struct imx_sc_ipc *handle;
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int id;
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};
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static void
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imx8qm_ldb_ch_set_bus_format(struct imx8qm_ldb_channel *imx8qm_ldb_ch,
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u32 bus_format)
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{
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struct imx8qm_ldb *imx8qm_ldb = imx8qm_ldb_ch->imx8qm_ldb;
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struct ldb *ldb = &imx8qm_ldb->base;
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struct ldb_channel *ldb_ch = &imx8qm_ldb_ch->base;
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switch (bus_format) {
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case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
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if (ldb_ch->chno == 0 || ldb->dual)
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ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT;
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if (ldb_ch->chno == 1 || ldb->dual)
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ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT;
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
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if (ldb_ch->chno == 0 || ldb->dual)
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ldb->ldb_ctrl |= LDB_CH0_DATA_WIDTH_24BIT;
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if (ldb_ch->chno == 1 || ldb->dual)
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ldb->ldb_ctrl |= LDB_CH1_DATA_WIDTH_24BIT;
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break;
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case MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG:
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if (ldb_ch->chno == 0 || ldb->dual)
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ldb->ldb_ctrl |= LDB_CH0_10BIT_EN |
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LDB_CH0_DATA_WIDTH_30BIT;
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if (ldb_ch->chno == 1 || ldb->dual)
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ldb->ldb_ctrl |= LDB_CH1_10BIT_EN |
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LDB_CH1_DATA_WIDTH_30BIT;
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break;
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case MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA:
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if (ldb_ch->chno == 0 || ldb->dual)
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ldb->ldb_ctrl |= LDB_CH0_10BIT_EN |
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LDB_CH0_DATA_WIDTH_30BIT |
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LDB_BIT_MAP_CH0_JEIDA;
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if (ldb_ch->chno == 1 || ldb->dual)
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ldb->ldb_ctrl |= LDB_CH1_10BIT_EN |
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LDB_CH1_DATA_WIDTH_30BIT |
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LDB_BIT_MAP_CH1_JEIDA;
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break;
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}
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}
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static struct drm_encoder *imx8qm_ldb_connector_best_encoder(
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struct drm_connector *connector)
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{
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struct imx8qm_ldb_channel *imx8qm_ldb_ch =
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con_to_imx8qm_ldb_ch(connector);
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return &imx8qm_ldb_ch->encoder;
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}
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static void imx8qm_ldb_pxlink_set_mst_valid(struct imx8qm_ldb *imx8qm_ldb,
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int dc_id, bool enable)
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{
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u32 rsc = dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0;
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imx_sc_misc_set_control(imx8qm_ldb->handle,
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rsc, IMX_SC_C_PXL_LINK_MST2_VLD, enable);
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}
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static void imx8qm_ldb_pxlink_set_sync_ctrl(struct imx8qm_ldb *imx8qm_ldb,
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int dc_id, bool enable)
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{
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u32 rsc = dc_id ? IMX_SC_R_DC_1 : IMX_SC_R_DC_0;
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imx_sc_misc_set_control(imx8qm_ldb->handle,
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rsc, IMX_SC_C_SYNC_CTRL1, enable);
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}
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static void imx8qm_ldb_encoder_enable(struct drm_encoder *encoder)
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{
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struct imx8qm_ldb_channel *imx8qm_ldb_ch =
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enc_to_imx8qm_ldb_ch(encoder);
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struct imx8qm_ldb *imx8qm_ldb = imx8qm_ldb_ch->imx8qm_ldb;
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struct ldb *ldb = &imx8qm_ldb->base;
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clk_prepare_enable(imx8qm_ldb->clk_pixel);
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clk_prepare_enable(imx8qm_ldb->clk_bypass);
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if (imx8qm_ldb_ch == &imx8qm_ldb->channel[0] || ldb->dual) {
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ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
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ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
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}
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if (imx8qm_ldb_ch == &imx8qm_ldb->channel[1] || ldb->dual) {
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ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
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ldb->ldb_ctrl |= ldb->dual ?
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LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1;
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}
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if (ldb->dual) {
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phy_power_on(imx8qm_ldb->channel[0].phy);
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phy_power_on(imx8qm_ldb->channel[1].phy);
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imx8qm_ldb->channel[0].phy_is_on = true;
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imx8qm_ldb->channel[1].phy_is_on = true;
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} else {
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phy_power_on(imx8qm_ldb_ch->phy);
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imx8qm_ldb_ch->phy_is_on = true;
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}
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imx8qm_ldb_pxlink_set_mst_valid(imx8qm_ldb, imx8qm_ldb->id, true);
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imx8qm_ldb_pxlink_set_sync_ctrl(imx8qm_ldb, imx8qm_ldb->id, true);
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}
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static void
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imx8qm_ldb_encoder_atomic_mode_set(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *connector_state)
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{
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struct imx8qm_ldb_channel *imx8qm_ldb_ch =
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enc_to_imx8qm_ldb_ch(encoder);
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struct imx8qm_ldb *imx8qm_ldb = imx8qm_ldb_ch->imx8qm_ldb;
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struct ldb_channel *ldb_ch = &imx8qm_ldb_ch->base;
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struct ldb *ldb = &imx8qm_ldb->base;
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struct drm_display_mode *mode = &crtc_state->adjusted_mode;
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unsigned long di_clk = mode->clock * 1000;
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if (mode->clock > 300000) {
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dev_warn(ldb->dev,
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"%s: mode exceeds 300 MHz pixel clock\n", __func__);
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}
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if (mode->clock > 150000 && !ldb->dual) {
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dev_warn(ldb->dev,
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"%s: mode exceeds 150 MHz pixel clock\n", __func__);
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}
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clk_set_rate(imx8qm_ldb->clk_bypass, di_clk);
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clk_set_rate(imx8qm_ldb->clk_pixel, di_clk);
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if (ldb->dual) {
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mixel_phy_lvds_set_phy_speed(imx8qm_ldb->channel[0].phy,
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di_clk / 2);
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mixel_phy_lvds_set_phy_speed(imx8qm_ldb->channel[1].phy,
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di_clk / 2);
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} else {
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mixel_phy_lvds_set_phy_speed(imx8qm_ldb_ch->phy, di_clk);
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}
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if (ldb->dual) {
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/* VSYNC */
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if (mode->flags & DRM_MODE_FLAG_NVSYNC) {
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mixel_phy_lvds_set_vsync_pol(imx8qm_ldb->channel[0].phy,
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false);
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mixel_phy_lvds_set_vsync_pol(imx8qm_ldb->channel[1].phy,
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false);
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} else if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
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mixel_phy_lvds_set_vsync_pol(imx8qm_ldb->channel[0].phy,
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true);
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mixel_phy_lvds_set_vsync_pol(imx8qm_ldb->channel[1].phy,
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true);
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}
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/* HSYNC */
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if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
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mixel_phy_lvds_set_hsync_pol(imx8qm_ldb->channel[0].phy,
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false);
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mixel_phy_lvds_set_hsync_pol(imx8qm_ldb->channel[1].phy,
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false);
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} else if (mode->flags & DRM_MODE_FLAG_PHSYNC) {
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mixel_phy_lvds_set_hsync_pol(imx8qm_ldb->channel[0].phy,
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true);
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mixel_phy_lvds_set_hsync_pol(imx8qm_ldb->channel[1].phy,
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true);
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}
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} else {
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/* VSYNC */
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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mixel_phy_lvds_set_vsync_pol(imx8qm_ldb_ch->phy, false);
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else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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mixel_phy_lvds_set_vsync_pol(imx8qm_ldb_ch->phy, true);
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/* HSYNC */
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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mixel_phy_lvds_set_hsync_pol(imx8qm_ldb_ch->phy, false);
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else if (mode->flags & DRM_MODE_FLAG_PHSYNC)
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mixel_phy_lvds_set_hsync_pol(imx8qm_ldb_ch->phy, true);
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}
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if (!ldb_ch->bus_format) {
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struct drm_connector *connector = connector_state->connector;
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struct drm_display_info *di = &connector->display_info;
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if (di->num_bus_formats)
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ldb_ch->bus_format = di->bus_formats[0];
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}
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imx8qm_ldb_ch_set_bus_format(imx8qm_ldb_ch, ldb_ch->bus_format);
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}
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static void imx8qm_ldb_encoder_disable(struct drm_encoder *encoder)
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{
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struct imx8qm_ldb_channel *imx8qm_ldb_ch =
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enc_to_imx8qm_ldb_ch(encoder);
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struct imx8qm_ldb *imx8qm_ldb = imx8qm_ldb_ch->imx8qm_ldb;
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struct ldb *ldb = &imx8qm_ldb->base;
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imx8qm_ldb_pxlink_set_mst_valid(imx8qm_ldb, imx8qm_ldb->id, false);
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imx8qm_ldb_pxlink_set_sync_ctrl(imx8qm_ldb, imx8qm_ldb->id, false);
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if (ldb->dual) {
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phy_power_off(imx8qm_ldb->channel[0].phy);
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phy_power_off(imx8qm_ldb->channel[1].phy);
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imx8qm_ldb->channel[0].phy_is_on = false;
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imx8qm_ldb->channel[1].phy_is_on = false;
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} else {
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phy_power_off(imx8qm_ldb_ch->phy);
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imx8qm_ldb_ch->phy_is_on = false;
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}
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clk_disable_unprepare(imx8qm_ldb->clk_bypass);
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clk_disable_unprepare(imx8qm_ldb->clk_pixel);
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}
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static int
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imx8qm_ldb_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
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struct imx8qm_ldb_channel *imx8qm_ldb_ch =
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enc_to_imx8qm_ldb_ch(encoder);
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struct ldb_channel *ldb_ch = &imx8qm_ldb_ch->base;
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struct drm_display_info *di = &conn_state->connector->display_info;
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u32 bus_format = ldb_ch->bus_format;
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/* Bus format description in DT overrides connector display info. */
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if (!bus_format && di->num_bus_formats) {
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bus_format = di->bus_formats[0];
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imx_crtc_state->bus_flags = di->bus_flags;
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} else {
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bus_format = ldb_ch->bus_format;
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imx_crtc_state->bus_flags = imx8qm_ldb_ch->bus_flags;
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}
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switch (bus_format) {
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case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
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imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB666_1X30_PADLO;
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
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case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
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imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB888_1X30_PADLO;
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break;
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case MEDIA_BUS_FMT_RGB101010_1X7X5_SPWG:
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case MEDIA_BUS_FMT_RGB101010_1X7X5_JEIDA:
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imx_crtc_state->bus_format = MEDIA_BUS_FMT_RGB101010_1X30;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct drm_connector_funcs imx8qm_ldb_connector_funcs = {
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = imx_drm_connector_destroy,
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.reset = drm_atomic_helper_connector_reset,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
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};
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static const struct drm_connector_helper_funcs
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imx8qm_ldb_connector_helper_funcs = {
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.best_encoder = imx8qm_ldb_connector_best_encoder,
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};
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static const struct drm_encoder_funcs imx8qm_ldb_encoder_funcs = {
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.destroy = imx_drm_encoder_destroy,
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};
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static const struct drm_encoder_helper_funcs imx8qm_ldb_encoder_helper_funcs = {
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.atomic_mode_set = imx8qm_ldb_encoder_atomic_mode_set,
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.enable = imx8qm_ldb_encoder_enable,
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.disable = imx8qm_ldb_encoder_disable,
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.atomic_check = imx8qm_ldb_encoder_atomic_check,
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};
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static const struct of_device_id imx8qm_ldb_dt_ids[] = {
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{ .compatible = "fsl,imx8qm-ldb", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, imx8qm_ldb_dt_ids);
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static int
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imx8qm_ldb_bind(struct device *dev, struct device *master, void *data)
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{
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struct drm_device *drm = data;
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struct device_node *np = dev->of_node;
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struct device_node *child;
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struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
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struct ldb *ldb;
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struct ldb_channel *ldb_ch;
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struct drm_encoder *encoder[LDB_CH_NUM];
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int ret;
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int i;
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ldb = &imx8qm_ldb->base;
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ldb->dev = dev;
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ldb->ctrl_reg = 0xe0;
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ldb->output_port = 1;
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for (i = 0; i < LDB_CH_NUM; i++) {
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imx8qm_ldb->channel[i].imx8qm_ldb = imx8qm_ldb;
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ldb->channel[i] = &imx8qm_ldb->channel[i].base;
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}
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ret = imx_scu_get_handle(&imx8qm_ldb->handle);
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if (ret) {
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dev_err(dev, "failed to get scu ipc handle %d\n", ret);
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return ret;
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}
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imx8qm_ldb->id = of_alias_get_id(np, "ldb");
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imx8qm_ldb->clk_pixel = devm_clk_get(dev, "pixel");
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if (IS_ERR(imx8qm_ldb->clk_pixel))
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return PTR_ERR(imx8qm_ldb->clk_pixel);
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imx8qm_ldb->clk_bypass = devm_clk_get(dev, "bypass");
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if (IS_ERR(imx8qm_ldb->clk_bypass))
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return PTR_ERR(imx8qm_ldb->clk_bypass);
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for (i = 0; i < LDB_CH_NUM; i++) {
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encoder[i] = &imx8qm_ldb->channel[i].encoder;
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drm_encoder_helper_add(encoder[i],
|
|
&imx8qm_ldb_encoder_helper_funcs);
|
|
drm_encoder_init(drm, encoder[i], &imx8qm_ldb_encoder_funcs,
|
|
DRM_MODE_ENCODER_LVDS, NULL);
|
|
}
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = ldb_bind(ldb, encoder);
|
|
if (ret)
|
|
goto disable_pm_runtime;
|
|
|
|
for_each_child_of_node(np, child) {
|
|
struct imx8qm_ldb_channel *imx8qm_ldb_ch;
|
|
bool auxiliary_ch = false;
|
|
|
|
ret = of_property_read_u32(child, "reg", &i);
|
|
if (ret || i < 0 || i > 1) {
|
|
ret = -EINVAL;
|
|
goto free_child;
|
|
}
|
|
|
|
if (ldb->dual && i > 0) {
|
|
auxiliary_ch = true;
|
|
imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
|
|
goto get_phy;
|
|
}
|
|
|
|
if (!of_device_is_available(child))
|
|
continue;
|
|
|
|
imx8qm_ldb_ch = &imx8qm_ldb->channel[i];
|
|
get_phy:
|
|
imx8qm_ldb_ch->phy = devm_of_phy_get(dev, child, "ldb_phy");
|
|
if (IS_ERR(imx8qm_ldb_ch->phy)) {
|
|
ret = PTR_ERR(imx8qm_ldb_ch->phy);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "can't get channel%d phy: %d\n",
|
|
i, ret);
|
|
goto free_child;
|
|
}
|
|
|
|
ret = phy_init(imx8qm_ldb_ch->phy);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to initialize channel%d phy: %d\n",
|
|
i, ret);
|
|
goto free_child;
|
|
}
|
|
|
|
if (auxiliary_ch)
|
|
continue;
|
|
}
|
|
|
|
for (i = 0; i < LDB_CH_NUM; i++) {
|
|
ldb_ch = &imx8qm_ldb->channel[i].base;
|
|
if (!ldb_ch->is_valid) {
|
|
drm_encoder_cleanup(encoder[i]);
|
|
continue;
|
|
}
|
|
|
|
ret = imx_drm_encoder_parse_of(drm, encoder[i], ldb_ch->child);
|
|
if (ret)
|
|
goto disable_pm_runtime;
|
|
}
|
|
|
|
return 0;
|
|
|
|
free_child:
|
|
of_node_put(child);
|
|
disable_pm_runtime:
|
|
pm_runtime_disable(dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void imx8qm_ldb_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < LDB_CH_NUM; i++) {
|
|
struct imx8qm_ldb_channel *imx8qm_ldb_ch =
|
|
&imx8qm_ldb->channel[i];
|
|
|
|
if (imx8qm_ldb_ch->phy_is_on)
|
|
phy_power_off(imx8qm_ldb_ch->phy);
|
|
|
|
phy_exit(imx8qm_ldb_ch->phy);
|
|
}
|
|
|
|
pm_runtime_disable(dev);
|
|
}
|
|
|
|
static const struct component_ops imx8qm_ldb_ops = {
|
|
.bind = imx8qm_ldb_bind,
|
|
.unbind = imx8qm_ldb_unbind,
|
|
};
|
|
|
|
static int imx8qm_ldb_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct imx8qm_ldb *imx8qm_ldb;
|
|
|
|
imx8qm_ldb = devm_kzalloc(dev, sizeof(*imx8qm_ldb), GFP_KERNEL);
|
|
if (!imx8qm_ldb)
|
|
return -ENOMEM;
|
|
|
|
dev_set_drvdata(dev, imx8qm_ldb);
|
|
|
|
return component_add(dev, &imx8qm_ldb_ops);
|
|
}
|
|
|
|
static int imx8qm_ldb_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &imx8qm_ldb_ops);
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int imx8qm_ldb_suspend(struct device *dev)
|
|
{
|
|
struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
if (imx8qm_ldb == NULL)
|
|
return 0;
|
|
|
|
for (i = 0; i < LDB_CH_NUM; i++)
|
|
phy_exit(imx8qm_ldb->channel[i].phy);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int imx8qm_ldb_resume(struct device *dev)
|
|
{
|
|
struct imx8qm_ldb *imx8qm_ldb = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
if (imx8qm_ldb == NULL)
|
|
return 0;
|
|
|
|
for (i = 0; i < LDB_CH_NUM; i++)
|
|
phy_init(imx8qm_ldb->channel[i].phy);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops imx8qm_ldb_pm_ops = {
|
|
SET_LATE_SYSTEM_SLEEP_PM_OPS(imx8qm_ldb_suspend, imx8qm_ldb_resume)
|
|
};
|
|
|
|
static struct platform_driver imx8qm_ldb_driver = {
|
|
.probe = imx8qm_ldb_probe,
|
|
.remove = imx8qm_ldb_remove,
|
|
.driver = {
|
|
.of_match_table = imx8qm_ldb_dt_ids,
|
|
.name = DRIVER_NAME,
|
|
.pm = &imx8qm_ldb_pm_ops,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(imx8qm_ldb_driver);
|
|
|
|
MODULE_DESCRIPTION("i.MX8QM LVDS driver");
|
|
MODULE_AUTHOR("Freescale Semiconductor, Inc.");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|