The bit DIV0 of register STORE9_STATIC is used as a control bit
to fix the unsynchronization issue bewteen two display streams
in FrameGen side-by-side mode, which is introduced from an ECO
operation for the display controller. The bit has to be one
when the side-by-side mode is enabled. And, it has to be zero
when the mode is disabled, otherwise, a single display stream
cannot startup correctly. Since the DPU common driver initializes
the register for us at the driver probe stage and system resume
stage, we may remove the same initialization logic of our own.
Without this patch, as the DPU blit engine DRM driver is resumed
relatively late, the bit would be overwritten to be zero at the
driver's ->resume() callback, which causes the display controller
cannot be correctly resumed from FrameGen side-by-side mode and
content ExtDst shadow load done event from the slave stream won't
come.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
d3cf551985