589 lines
18 KiB
C
589 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2011 Freescale Semiconductor, Inc
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*
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* Freescale Integrated Flash Controller
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*
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* Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/fsl_ifc.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
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EXPORT_SYMBOL(fsl_ifc_ctrl_dev);
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#define FSL_IFC_V1_3_0 0x01030000
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#define IFC_TIMEOUT_MSECS 1000 /* 1000ms */
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/*
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* convert_ifc_address - convert the base address
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* @addr_base: base address of the memory bank
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*/
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unsigned int convert_ifc_address(phys_addr_t addr_base)
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{
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return addr_base & CSPR_BA;
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}
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EXPORT_SYMBOL(convert_ifc_address);
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/*
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* fsl_ifc_find - find IFC bank
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* @addr_base: base address of the memory bank
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*
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* This function walks IFC banks comparing "Base address" field of the CSPR
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* registers with the supplied addr_base argument. When bases match this
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* function returns bank number (starting with 0), otherwise it returns
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* appropriate errno value.
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*/
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int fsl_ifc_find(phys_addr_t addr_base)
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{
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int i = 0;
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if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs)
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return -ENODEV;
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for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) {
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u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr);
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if (cspr & CSPR_V && (cspr & CSPR_BA) ==
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convert_ifc_address(addr_base))
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return i;
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}
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return -ENOENT;
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}
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EXPORT_SYMBOL(fsl_ifc_find);
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static int fsl_ifc_ctrl_init(struct fsl_ifc_ctrl *ctrl)
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{
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struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
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/*
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* Clear all the common status and event registers
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*/
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if (ifc_in32(&ifc->cm_evter_stat) & IFC_CM_EVTER_STAT_CSER)
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ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
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/* enable all error and events */
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ifc_out32(IFC_CM_EVTER_EN_CSEREN, &ifc->cm_evter_en);
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/* enable all error and event interrupts */
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ifc_out32(IFC_CM_EVTER_INTR_EN_CSERIREN, &ifc->cm_evter_intr_en);
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ifc_out32(0x0, &ifc->cm_erattr0);
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ifc_out32(0x0, &ifc->cm_erattr1);
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return 0;
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}
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static int fsl_ifc_ctrl_remove(struct platform_device *dev)
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{
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struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(&dev->dev);
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free_irq(ctrl->nand_irq, ctrl);
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free_irq(ctrl->irq, ctrl);
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irq_dispose_mapping(ctrl->nand_irq);
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irq_dispose_mapping(ctrl->irq);
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iounmap(ctrl->gregs);
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dev_set_drvdata(&dev->dev, NULL);
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kfree(ctrl);
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return 0;
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}
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/*
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* NAND events are split between an operational interrupt which only
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* receives OPC, and an error interrupt that receives everything else,
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* including non-NAND errors. Whichever interrupt gets to it first
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* records the status and wakes the wait queue.
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*/
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static DEFINE_SPINLOCK(nand_irq_lock);
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static u32 check_nand_stat(struct fsl_ifc_ctrl *ctrl)
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{
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struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
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unsigned long flags;
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u32 stat;
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spin_lock_irqsave(&nand_irq_lock, flags);
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stat = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
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if (stat) {
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ifc_out32(stat, &ifc->ifc_nand.nand_evter_stat);
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ctrl->nand_stat = stat;
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wake_up(&ctrl->nand_wait);
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}
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spin_unlock_irqrestore(&nand_irq_lock, flags);
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return stat;
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}
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static irqreturn_t fsl_ifc_nand_irq(int irqno, void *data)
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{
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struct fsl_ifc_ctrl *ctrl = data;
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if (check_nand_stat(ctrl))
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return IRQ_HANDLED;
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return IRQ_NONE;
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}
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/*
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* NOTE: This interrupt is used to report ifc events of various kinds,
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* such as transaction errors on the chipselects.
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*/
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static irqreturn_t fsl_ifc_ctrl_irq(int irqno, void *data)
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{
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struct fsl_ifc_ctrl *ctrl = data;
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struct fsl_ifc_global __iomem *ifc = ctrl->gregs;
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u32 err_axiid, err_srcid, status, cs_err, err_addr;
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irqreturn_t ret = IRQ_NONE;
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/* read for chip select error */
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cs_err = ifc_in32(&ifc->cm_evter_stat);
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if (cs_err) {
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dev_err(ctrl->dev, "transaction sent to IFC is not mapped to"
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"any memory bank 0x%08X\n", cs_err);
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/* clear the chip select error */
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ifc_out32(IFC_CM_EVTER_STAT_CSER, &ifc->cm_evter_stat);
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/* read error attribute registers print the error information */
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status = ifc_in32(&ifc->cm_erattr0);
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err_addr = ifc_in32(&ifc->cm_erattr1);
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if (status & IFC_CM_ERATTR0_ERTYP_READ)
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dev_err(ctrl->dev, "Read transaction error"
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"CM_ERATTR0 0x%08X\n", status);
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else
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dev_err(ctrl->dev, "Write transaction error"
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"CM_ERATTR0 0x%08X\n", status);
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err_axiid = (status & IFC_CM_ERATTR0_ERAID) >>
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IFC_CM_ERATTR0_ERAID_SHIFT;
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dev_err(ctrl->dev, "AXI ID of the error"
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"transaction 0x%08X\n", err_axiid);
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err_srcid = (status & IFC_CM_ERATTR0_ESRCID) >>
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IFC_CM_ERATTR0_ESRCID_SHIFT;
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dev_err(ctrl->dev, "SRC ID of the error"
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"transaction 0x%08X\n", err_srcid);
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dev_err(ctrl->dev, "Transaction Address corresponding to error"
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"ERADDR 0x%08X\n", err_addr);
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ret = IRQ_HANDLED;
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}
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if (check_nand_stat(ctrl))
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ret = IRQ_HANDLED;
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return ret;
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}
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/*
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* fsl_ifc_ctrl_probe
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*
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* called by device layer when it finds a device matching
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* one our driver can handled. This code allocates all of
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* the resources needed for the controller only. The
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* resources for the NAND banks themselves are allocated
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* in the chip probe function.
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*/
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static int fsl_ifc_ctrl_probe(struct platform_device *dev)
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{
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int ret = 0;
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int version, banks;
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void __iomem *addr;
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dev_info(&dev->dev, "Freescale Integrated Flash Controller\n");
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fsl_ifc_ctrl_dev = kzalloc(sizeof(*fsl_ifc_ctrl_dev), GFP_KERNEL);
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if (!fsl_ifc_ctrl_dev)
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return -ENOMEM;
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dev_set_drvdata(&dev->dev, fsl_ifc_ctrl_dev);
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/* IOMAP the entire IFC region */
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fsl_ifc_ctrl_dev->gregs = of_iomap(dev->dev.of_node, 0);
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if (!fsl_ifc_ctrl_dev->gregs) {
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dev_err(&dev->dev, "failed to get memory region\n");
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ret = -ENODEV;
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goto err;
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}
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if (of_property_read_bool(dev->dev.of_node, "little-endian")) {
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fsl_ifc_ctrl_dev->little_endian = true;
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dev_dbg(&dev->dev, "IFC REGISTERS are LITTLE endian\n");
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} else {
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fsl_ifc_ctrl_dev->little_endian = false;
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dev_dbg(&dev->dev, "IFC REGISTERS are BIG endian\n");
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}
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version = ifc_in32(&fsl_ifc_ctrl_dev->gregs->ifc_rev) &
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FSL_IFC_VERSION_MASK;
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banks = (version == FSL_IFC_VERSION_1_0_0) ? 4 : 8;
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dev_info(&dev->dev, "IFC version %d.%d, %d banks\n",
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version >> 24, (version >> 16) & 0xf, banks);
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fsl_ifc_ctrl_dev->version = version;
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fsl_ifc_ctrl_dev->banks = banks;
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addr = fsl_ifc_ctrl_dev->gregs;
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if (version >= FSL_IFC_VERSION_2_0_0)
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addr += PGOFFSET_64K;
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else
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addr += PGOFFSET_4K;
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fsl_ifc_ctrl_dev->rregs = addr;
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/* get the Controller level irq */
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fsl_ifc_ctrl_dev->irq = irq_of_parse_and_map(dev->dev.of_node, 0);
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if (fsl_ifc_ctrl_dev->irq == 0) {
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dev_err(&dev->dev, "failed to get irq resource "
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"for IFC\n");
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ret = -ENODEV;
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goto err;
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}
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/* get the nand machine irq */
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fsl_ifc_ctrl_dev->nand_irq =
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irq_of_parse_and_map(dev->dev.of_node, 1);
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fsl_ifc_ctrl_dev->dev = &dev->dev;
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ret = fsl_ifc_ctrl_init(fsl_ifc_ctrl_dev);
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if (ret < 0)
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goto err;
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init_waitqueue_head(&fsl_ifc_ctrl_dev->nand_wait);
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ret = request_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_irq, IRQF_SHARED,
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"fsl-ifc", fsl_ifc_ctrl_dev);
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if (ret != 0) {
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dev_err(&dev->dev, "failed to install irq (%d)\n",
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fsl_ifc_ctrl_dev->irq);
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goto err_irq;
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}
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if (fsl_ifc_ctrl_dev->nand_irq) {
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ret = request_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_nand_irq,
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0, "fsl-ifc-nand", fsl_ifc_ctrl_dev);
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if (ret != 0) {
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dev_err(&dev->dev, "failed to install irq (%d)\n",
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fsl_ifc_ctrl_dev->nand_irq);
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goto err_nandirq;
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}
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}
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return 0;
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err_nandirq:
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free_irq(fsl_ifc_ctrl_dev->nand_irq, fsl_ifc_ctrl_dev);
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irq_dispose_mapping(fsl_ifc_ctrl_dev->nand_irq);
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err_irq:
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free_irq(fsl_ifc_ctrl_dev->irq, fsl_ifc_ctrl_dev);
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irq_dispose_mapping(fsl_ifc_ctrl_dev->irq);
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err:
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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/* save ifc registers */
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static int fsl_ifc_suspend(struct device *dev)
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{
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struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
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struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
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struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
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__be32 nand_evter_intr_en, cm_evter_intr_en, nor_evter_intr_en,
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gpcm_evter_intr_en;
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uint32_t ifc_bank, i;
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ctrl->saved_gregs = kzalloc(sizeof(struct fsl_ifc_global), GFP_KERNEL);
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if (!ctrl->saved_gregs)
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return -ENOMEM;
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ctrl->saved_rregs = kzalloc(sizeof(struct fsl_ifc_runtime), GFP_KERNEL);
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if (!ctrl->saved_rregs)
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return -ENOMEM;
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cm_evter_intr_en = ifc_in32(&fcm->cm_evter_intr_en);
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nand_evter_intr_en = ifc_in32(&runtime->ifc_nand.nand_evter_intr_en);
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nor_evter_intr_en = ifc_in32(&runtime->ifc_nor.nor_evter_intr_en);
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gpcm_evter_intr_en = ifc_in32(&runtime->ifc_gpcm.gpcm_evter_intr_en);
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/* IFC interrupts disabled */
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ifc_out32(0x0, &fcm->cm_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
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ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
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if (ctrl->saved_gregs) {
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for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
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ctrl->saved_gregs->cspr_cs[ifc_bank].cspr_ext =
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ifc_in32(&fcm->cspr_cs[ifc_bank].cspr_ext);
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ctrl->saved_gregs->cspr_cs[ifc_bank].cspr =
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ifc_in32(&fcm->cspr_cs[ifc_bank].cspr);
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ctrl->saved_gregs->amask_cs[ifc_bank].amask =
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ifc_in32(&fcm->amask_cs[ifc_bank].amask);
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ctrl->saved_gregs->csor_cs[ifc_bank].csor_ext =
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ifc_in32(&fcm->csor_cs[ifc_bank].csor_ext);
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ctrl->saved_gregs->csor_cs[ifc_bank].csor =
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ifc_in32(&fcm->csor_cs[ifc_bank].csor);
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for (i = 0; i < 4; i++) {
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ctrl->saved_gregs->ftim_cs[ifc_bank].ftim[i] =
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ifc_in32(
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&fcm->ftim_cs[ifc_bank].ftim[i]);
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}
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}
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ctrl->saved_gregs->rb_map = ifc_in32(&fcm->rb_map);
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ctrl->saved_gregs->wb_map = ifc_in32(&fcm->wb_map);
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ctrl->saved_gregs->ifc_gcr = ifc_in32(&fcm->ifc_gcr);
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ctrl->saved_gregs->ddr_ccr_low = ifc_in32(&fcm->ddr_ccr_low);
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ctrl->saved_gregs->cm_evter_en = ifc_in32(&fcm->cm_evter_en);
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}
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if (ctrl->saved_rregs) {
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/* IFC controller NAND machine registers */
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ctrl->saved_rregs->ifc_nand.ncfgr =
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ifc_in32(&runtime->ifc_nand.ncfgr);
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ctrl->saved_rregs->ifc_nand.nand_fcr0 =
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ifc_in32(&runtime->ifc_nand.nand_fcr0);
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ctrl->saved_rregs->ifc_nand.nand_fcr1 =
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ifc_in32(&runtime->ifc_nand.nand_fcr1);
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ctrl->saved_rregs->ifc_nand.row0 =
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ifc_in32(&runtime->ifc_nand.row0);
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ctrl->saved_rregs->ifc_nand.row1 =
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ifc_in32(&runtime->ifc_nand.row1);
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ctrl->saved_rregs->ifc_nand.col0 =
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ifc_in32(&runtime->ifc_nand.col0);
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ctrl->saved_rregs->ifc_nand.col1 =
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ifc_in32(&runtime->ifc_nand.col1);
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ctrl->saved_rregs->ifc_nand.row2 =
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ifc_in32(&runtime->ifc_nand.row2);
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ctrl->saved_rregs->ifc_nand.col2 =
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ifc_in32(&runtime->ifc_nand.col2);
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ctrl->saved_rregs->ifc_nand.row3 =
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ifc_in32(&runtime->ifc_nand.row3);
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ctrl->saved_rregs->ifc_nand.col3 =
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ifc_in32(&runtime->ifc_nand.col3);
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ctrl->saved_rregs->ifc_nand.nand_fbcr =
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ifc_in32(&runtime->ifc_nand.nand_fbcr);
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ctrl->saved_rregs->ifc_nand.nand_fir0 =
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ifc_in32(&runtime->ifc_nand.nand_fir0);
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ctrl->saved_rregs->ifc_nand.nand_fir1 =
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ifc_in32(&runtime->ifc_nand.nand_fir1);
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ctrl->saved_rregs->ifc_nand.nand_fir2 =
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ifc_in32(&runtime->ifc_nand.nand_fir2);
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ctrl->saved_rregs->ifc_nand.nand_csel =
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ifc_in32(&runtime->ifc_nand.nand_csel);
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ctrl->saved_rregs->ifc_nand.nandseq_strt =
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ifc_in32(
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&runtime->ifc_nand.nandseq_strt);
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ctrl->saved_rregs->ifc_nand.nand_evter_en =
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ifc_in32(
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&runtime->ifc_nand.nand_evter_en);
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ctrl->saved_rregs->ifc_nand.nanndcr =
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ifc_in32(&runtime->ifc_nand.nanndcr);
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ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg0 =
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ifc_in32(
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&runtime->ifc_nand.nand_dll_lowcfg0);
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ctrl->saved_rregs->ifc_nand.nand_dll_lowcfg1 =
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ifc_in32(
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&runtime->ifc_nand.nand_dll_lowcfg1);
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/* IFC controller NOR machine registers */
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ctrl->saved_rregs->ifc_nor.nor_evter_en =
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ifc_in32(
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&runtime->ifc_nor.nor_evter_en);
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ctrl->saved_rregs->ifc_nor.norcr =
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ifc_in32(&runtime->ifc_nor.norcr);
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/* IFC controller GPCM Machine registers */
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ctrl->saved_rregs->ifc_gpcm.gpcm_evter_en =
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ifc_in32(
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&runtime->ifc_gpcm.gpcm_evter_en);
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}
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/* save the interrupt values */
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ctrl->saved_gregs->cm_evter_intr_en = cm_evter_intr_en;
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ctrl->saved_rregs->ifc_nand.nand_evter_intr_en = nand_evter_intr_en;
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ctrl->saved_rregs->ifc_nor.nor_evter_intr_en = nor_evter_intr_en;
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ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en = gpcm_evter_intr_en;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* restore ifc registers */
|
|
static int fsl_ifc_resume(struct device *dev)
|
|
{
|
|
struct fsl_ifc_ctrl *ctrl = dev_get_drvdata(dev);
|
|
struct fsl_ifc_global __iomem *fcm = ctrl->gregs;
|
|
struct fsl_ifc_runtime __iomem *runtime = ctrl->rregs;
|
|
struct fsl_ifc_global *savd_gregs = ctrl->saved_gregs;
|
|
struct fsl_ifc_runtime *savd_rregs = ctrl->saved_rregs;
|
|
uint32_t ver = 0, ncfgr, timeout, ifc_bank, i;
|
|
|
|
/*
|
|
* IFC interrupts disabled
|
|
*/
|
|
ifc_out32(0x0, &fcm->cm_evter_intr_en);
|
|
ifc_out32(0x0, &runtime->ifc_nand.nand_evter_intr_en);
|
|
ifc_out32(0x0, &runtime->ifc_nor.nor_evter_intr_en);
|
|
ifc_out32(0x0, &runtime->ifc_gpcm.gpcm_evter_intr_en);
|
|
|
|
|
|
if (ctrl->saved_gregs) {
|
|
for (ifc_bank = 0; ifc_bank < FSL_IFC_BANK_COUNT; ifc_bank++) {
|
|
ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr_ext,
|
|
&fcm->cspr_cs[ifc_bank].cspr_ext);
|
|
ifc_out32(savd_gregs->cspr_cs[ifc_bank].cspr,
|
|
&fcm->cspr_cs[ifc_bank].cspr);
|
|
ifc_out32(savd_gregs->amask_cs[ifc_bank].amask,
|
|
&fcm->amask_cs[ifc_bank].amask);
|
|
ifc_out32(savd_gregs->csor_cs[ifc_bank].csor_ext,
|
|
&fcm->csor_cs[ifc_bank].csor_ext);
|
|
ifc_out32(savd_gregs->csor_cs[ifc_bank].csor,
|
|
&fcm->csor_cs[ifc_bank].csor);
|
|
for (i = 0; i < 4; i++) {
|
|
ifc_out32(savd_gregs->ftim_cs[ifc_bank].ftim[i],
|
|
&fcm->ftim_cs[ifc_bank].ftim[i]);
|
|
}
|
|
}
|
|
ifc_out32(savd_gregs->rb_map, &fcm->rb_map);
|
|
ifc_out32(savd_gregs->wb_map, &fcm->wb_map);
|
|
ifc_out32(savd_gregs->ifc_gcr, &fcm->ifc_gcr);
|
|
ifc_out32(savd_gregs->ddr_ccr_low, &fcm->ddr_ccr_low);
|
|
ifc_out32(savd_gregs->cm_evter_en, &fcm->cm_evter_en);
|
|
}
|
|
|
|
if (ctrl->saved_rregs) {
|
|
/* IFC controller NAND machine registers */
|
|
ifc_out32(savd_rregs->ifc_nand.ncfgr,
|
|
&runtime->ifc_nand.ncfgr);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_fcr0,
|
|
&runtime->ifc_nand.nand_fcr0);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_fcr1,
|
|
&runtime->ifc_nand.nand_fcr1);
|
|
ifc_out32(savd_rregs->ifc_nand.row0, &runtime->ifc_nand.row0);
|
|
ifc_out32(savd_rregs->ifc_nand.row1, &runtime->ifc_nand.row1);
|
|
ifc_out32(savd_rregs->ifc_nand.col0, &runtime->ifc_nand.col0);
|
|
ifc_out32(savd_rregs->ifc_nand.col1, &runtime->ifc_nand.col1);
|
|
ifc_out32(savd_rregs->ifc_nand.row2, &runtime->ifc_nand.row2);
|
|
ifc_out32(savd_rregs->ifc_nand.col2, &runtime->ifc_nand.col2);
|
|
ifc_out32(savd_rregs->ifc_nand.row3, &runtime->ifc_nand.row3);
|
|
ifc_out32(savd_rregs->ifc_nand.col3, &runtime->ifc_nand.col3);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_fbcr,
|
|
&runtime->ifc_nand.nand_fbcr);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_fir0,
|
|
&runtime->ifc_nand.nand_fir0);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_fir1,
|
|
&runtime->ifc_nand.nand_fir1);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_fir2,
|
|
&runtime->ifc_nand.nand_fir2);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_csel,
|
|
&runtime->ifc_nand.nand_csel);
|
|
ifc_out32(savd_rregs->ifc_nand.nandseq_strt,
|
|
&runtime->ifc_nand.nandseq_strt);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_evter_en,
|
|
&runtime->ifc_nand.nand_evter_en);
|
|
ifc_out32(savd_rregs->ifc_nand.nanndcr,
|
|
&runtime->ifc_nand.nanndcr);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg0,
|
|
&runtime->ifc_nand.nand_dll_lowcfg0);
|
|
ifc_out32(savd_rregs->ifc_nand.nand_dll_lowcfg1,
|
|
&runtime->ifc_nand.nand_dll_lowcfg1);
|
|
|
|
/* IFC controller NOR machine registers */
|
|
ifc_out32(savd_rregs->ifc_nor.nor_evter_en,
|
|
&runtime->ifc_nor.nor_evter_en);
|
|
ifc_out32(savd_rregs->ifc_nor.norcr, &runtime->ifc_nor.norcr);
|
|
|
|
/* IFC controller GPCM Machine registers */
|
|
ifc_out32(savd_rregs->ifc_gpcm.gpcm_evter_en,
|
|
&runtime->ifc_gpcm.gpcm_evter_en);
|
|
|
|
/* IFC interrupts enabled */
|
|
ifc_out32(ctrl->saved_gregs->cm_evter_intr_en,
|
|
&fcm->cm_evter_intr_en);
|
|
ifc_out32(ctrl->saved_rregs->ifc_nand.nand_evter_intr_en,
|
|
&runtime->ifc_nand.nand_evter_intr_en);
|
|
ifc_out32(ctrl->saved_rregs->ifc_nor.nor_evter_intr_en,
|
|
&runtime->ifc_nor.nor_evter_intr_en);
|
|
ifc_out32(ctrl->saved_rregs->ifc_gpcm.gpcm_evter_intr_en,
|
|
&runtime->ifc_gpcm.gpcm_evter_intr_en);
|
|
|
|
kfree(ctrl->saved_gregs);
|
|
kfree(ctrl->saved_rregs);
|
|
ctrl->saved_gregs = NULL;
|
|
ctrl->saved_rregs = NULL;
|
|
}
|
|
|
|
ver = ifc_in32(&fcm->ifc_rev);
|
|
ncfgr = ifc_in32(&runtime->ifc_nand.ncfgr);
|
|
if (ver >= FSL_IFC_V1_3_0) {
|
|
|
|
ifc_out32(ncfgr | IFC_NAND_NCFGR_SRAM_INIT_EN,
|
|
&runtime->ifc_nand.ncfgr);
|
|
/* wait for SRAM_INIT bit to be clear or timeout */
|
|
timeout = 10;
|
|
while ((ifc_in32(&runtime->ifc_nand.ncfgr) &
|
|
IFC_NAND_NCFGR_SRAM_INIT_EN) && timeout) {
|
|
mdelay(IFC_TIMEOUT_MSECS);
|
|
timeout--;
|
|
}
|
|
|
|
if (!timeout)
|
|
dev_err(ctrl->dev, "Timeout waiting for IFC SRAM INIT");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
static const struct of_device_id fsl_ifc_match[] = {
|
|
{
|
|
.compatible = "fsl,ifc",
|
|
},
|
|
{},
|
|
};
|
|
|
|
static const struct dev_pm_ops ifc_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(fsl_ifc_suspend, fsl_ifc_resume)
|
|
};
|
|
|
|
static struct platform_driver fsl_ifc_ctrl_driver = {
|
|
.driver = {
|
|
.name = "fsl-ifc",
|
|
.of_match_table = fsl_ifc_match,
|
|
.pm = &ifc_pm_ops,
|
|
},
|
|
.probe = fsl_ifc_ctrl_probe,
|
|
.remove = fsl_ifc_ctrl_remove,
|
|
};
|
|
|
|
static int __init fsl_ifc_init(void)
|
|
{
|
|
return platform_driver_register(&fsl_ifc_ctrl_driver);
|
|
}
|
|
subsys_initcall(fsl_ifc_init);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_AUTHOR("Freescale Semiconductor");
|
|
MODULE_DESCRIPTION("Freescale Integrated Flash Controller driver");
|