400 lines
11 KiB
C
400 lines
11 KiB
C
/*
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* IMX Display Mix GPR reset driver
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*
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* Copyright 2019 NXP
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/reset-controller.h>
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#include <dt-bindings/reset/imx8mm-dispmix.h>
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#include <dt-bindings/reset/imx8mn-dispmix.h>
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#define DRIVER_NAME "dispmix_reset_drv"
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/* DISPMIX GPR registers */
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#define DISPLAY_MIX_SFT_RSTN_CSR 0x00
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#define DISPLAY_MIX_CLK_EN_CSR 0x00
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#define GPR_MIPI_RESET_DIV 0x00
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struct dispmix_reset_controller {
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struct reset_controller_dev rcdev;
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struct device *dev;
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struct regmap *rstcon;
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struct clk *ipg_clk;
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bool active_low;
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};
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struct dispmix_reset_entry {
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uint32_t reg_off;
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uint32_t bit_off;
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};
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struct dispmix_reset_pdata {
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const struct dispmix_reset_entry *resets;
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uint32_t nr_resets;
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const struct regmap_config *config;
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};
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#define RESET_ENTRY(id, reg, bit) \
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[id] = { .reg_off = (reg), .bit_off = (bit) }
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static const struct dispmix_reset_entry imx8mm_sft_rstn[] = {
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/* dispmix reset entry */
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_CHIP_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 0),
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_HARD_ASYNC_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 1),
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_CSI_HRESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 2),
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RESET_ENTRY(IMX8MM_CAMERA_PIXEL_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 3),
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RESET_ENTRY(IMX8MM_MIPI_CSI_I_PRESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 4),
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RESET_ENTRY(IMX8MM_MIPI_DSI_I_PRESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 5),
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RESET_ENTRY(IMX8MM_BUS_RSTN_BLK_SYNC,
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DISPLAY_MIX_SFT_RSTN_CSR, 6),
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};
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static const struct dispmix_reset_entry imx8mm_clk_en[] = {
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/* dispmix clock enable entry */
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_CSI_HCLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 0),
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_SPU_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 1),
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_MEM_WRAPPER_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 2),
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 3),
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_S_EN,
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DISPLAY_MIX_CLK_EN_CSR, 4),
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RESET_ENTRY(IMX8MM_CSI_BRIDGE_IPG_CLK_S_RAW_EN,
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DISPLAY_MIX_CLK_EN_CSR, 5),
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RESET_ENTRY(IMX8MM_LCDIF_APB_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 6),
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RESET_ENTRY(IMX8MM_LCDIF_PIXEL_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 7),
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RESET_ENTRY(IMX8MM_MIPI_DSI_PCLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 8),
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RESET_ENTRY(IMX8MM_MIPI_DSI_CLKREF_EN,
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DISPLAY_MIX_CLK_EN_CSR, 9),
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RESET_ENTRY(IMX8MM_MIPI_CSI_ACLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 10),
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RESET_ENTRY(IMX8MM_MIPI_CSI_PCLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 11),
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RESET_ENTRY(IMX8MM_BUS_BLK_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 12),
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};
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static const struct dispmix_reset_entry imx8mm_mipi_rst[] = {
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/* mipi lanes reset entry */
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RESET_ENTRY(IMX8MM_MIPI_S_RESET,
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GPR_MIPI_RESET_DIV, 16),
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RESET_ENTRY(IMX8MM_MIPI_M_RESET,
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GPR_MIPI_RESET_DIV, 17),
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};
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static const struct dispmix_reset_entry imx8mn_sft_rstn[] = {
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/* dispmix reset entry */
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RESET_ENTRY(IMX8MN_MIPI_DSI_PCLK_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 0),
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RESET_ENTRY(IMX8MN_MIPI_DSI_CLKREF_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 1),
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RESET_ENTRY(IMX8MN_MIPI_CSI_PCLK_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 2),
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RESET_ENTRY(IMX8MN_MIPI_CSI_ACLK_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 3),
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RESET_ENTRY(IMX8MN_LCDIF_PIXEL_CLK_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 4),
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RESET_ENTRY(IMX8MN_LCDIF_APB_CLK_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 5),
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RESET_ENTRY(IMX8MN_ISI_PROC_CLK_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 6),
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RESET_ENTRY(IMX8MN_ISI_APB_CLK_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 7),
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RESET_ENTRY(IMX8MN_BUS_BLK_CLK_RESET,
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DISPLAY_MIX_SFT_RSTN_CSR, 8),
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};
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static const struct dispmix_reset_entry imx8mn_clk_en[] = {
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/* dispmix clock enable entry */
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RESET_ENTRY(IMX8MN_MIPI_DSI_PCLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 0),
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RESET_ENTRY(IMX8MN_MIPI_DSI_CLKREF_EN,
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DISPLAY_MIX_CLK_EN_CSR, 1),
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RESET_ENTRY(IMX8MN_MIPI_CSI_PCLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 2),
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RESET_ENTRY(IMX8MN_MIPI_CSI_ACLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 3),
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RESET_ENTRY(IMX8MN_LCDIF_PIXEL_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 4),
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RESET_ENTRY(IMX8MN_LCDIF_APB_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 5),
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RESET_ENTRY(IMX8MN_ISI_PROC_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 6),
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RESET_ENTRY(IMX8MN_ISI_APB_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 7),
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RESET_ENTRY(IMX8MN_BUS_BLK_CLK_EN,
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DISPLAY_MIX_CLK_EN_CSR, 8),
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};
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static const struct dispmix_reset_entry imx8mn_mipi_rst[] = {
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/* mipi lanes reset entry */
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RESET_ENTRY(IMX8MN_MIPI_S_RESET,
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GPR_MIPI_RESET_DIV, 16),
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RESET_ENTRY(IMX8MN_MIPI_M_RESET,
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GPR_MIPI_RESET_DIV, 17),
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};
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static const struct regmap_config sft_rstn_config = {
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.name = "sft_rstn",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x00,
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};
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static const struct regmap_config clk_en_config = {
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.name = "clk_en",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x00,
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};
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static const struct regmap_config mipi_rst_config = {
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.name = "mipi_rst",
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = 0x00,
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};
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static const struct dispmix_reset_pdata imx8mm_sft_rstn_pdata = {
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.resets = imx8mm_sft_rstn,
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.nr_resets = IMX8MM_DISPMIX_SFT_RSTN_NUM,
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.config = &sft_rstn_config,
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};
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static const struct dispmix_reset_pdata imx8mm_clk_en_pdata = {
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.resets = imx8mm_clk_en,
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.nr_resets = IMX8MM_DISPMIX_CLK_EN_NUM,
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.config = &clk_en_config,
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};
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static const struct dispmix_reset_pdata imx8mm_mipi_rst_pdata = {
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.resets = imx8mm_mipi_rst,
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.nr_resets = IMX8MM_MIPI_RESET_NUM,
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.config = &mipi_rst_config,
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};
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static const struct dispmix_reset_pdata imx8mn_sft_rstn_pdata = {
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.resets = imx8mn_sft_rstn,
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.nr_resets = IMX8MN_DISPMIX_SFT_RSTN_NUM,
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.config = &sft_rstn_config,
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};
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static const struct dispmix_reset_pdata imx8mn_clk_en_pdata = {
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.resets = imx8mn_clk_en,
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.nr_resets = IMX8MN_DISPMIX_CLK_EN_NUM,
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.config = &clk_en_config,
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};
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static const struct dispmix_reset_pdata imx8mn_mipi_rst_pdata = {
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.resets = imx8mn_mipi_rst,
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.nr_resets = IMX8MN_MIPI_RESET_NUM,
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.config = &mipi_rst_config,
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};
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static const struct of_device_id dispmix_reset_dt_ids[] = {
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{
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.compatible = "fsl,imx8mm-dispmix-sft-rstn",
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.data = &imx8mm_sft_rstn_pdata,
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},
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{
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.compatible = "fsl,imx8mm-dispmix-clk-en",
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.data = &imx8mm_clk_en_pdata,
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},
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{
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.compatible = "fsl,imx8mm-dispmix-mipi-rst",
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.data = &imx8mm_mipi_rst_pdata,
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},
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{
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.compatible = "fsl,imx8mn-dispmix-sft-rstn",
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.data = &imx8mn_sft_rstn_pdata,
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},
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{
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.compatible = "fsl,imx8mn-dispmix-clk-en",
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.data = &imx8mn_clk_en_pdata,
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},
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{
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.compatible = "fsl,imx8mn-dispmix-mipi-rst",
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.data = &imx8mn_mipi_rst_pdata,
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, dispmix_reset_dt_ids);
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static int dispmix_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct dispmix_reset_controller *drcdev;
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const struct of_device_id *of_id;
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const struct dispmix_reset_pdata *pdata;
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const struct dispmix_reset_entry *rstent;
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struct regmap *rstcon;
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if (id >= rcdev->nr_resets) {
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pr_info("dispmix reset: %lu is not a valid line\n", id);
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return -EINVAL;
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}
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drcdev = container_of(rcdev, struct dispmix_reset_controller, rcdev);
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of_id = of_match_device(dispmix_reset_dt_ids, drcdev->dev);
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pdata = of_id->data;
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rstcon = drcdev->rstcon;
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rstent = &pdata->resets[id];
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pm_runtime_get_sync(drcdev->dev);
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regmap_update_bits(rstcon, rstent->reg_off,
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1 << rstent->bit_off,
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!drcdev->active_low << rstent->bit_off);
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pm_runtime_put(drcdev->dev);
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return 0;
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}
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static int dispmix_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct dispmix_reset_controller *drcdev;
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const struct of_device_id *of_id;
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const struct dispmix_reset_pdata *pdata;
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const struct dispmix_reset_entry *rstent;
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struct regmap *rstcon;
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if (id >= rcdev->nr_resets) {
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pr_info("dispmix reset: %lu is not a valid line\n", id);
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return -EINVAL;
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}
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drcdev = container_of(rcdev, struct dispmix_reset_controller, rcdev);
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of_id = of_match_device(dispmix_reset_dt_ids, drcdev->dev);
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pdata = of_id->data;
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rstcon = drcdev->rstcon;
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rstent = &pdata->resets[id];
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pm_runtime_get_sync(drcdev->dev);
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regmap_update_bits(rstcon, rstent->reg_off,
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1 << rstent->bit_off,
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!!drcdev->active_low << rstent->bit_off);
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pm_runtime_put(drcdev->dev);
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return 0;
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}
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static const struct reset_control_ops dispmix_reset_ops = {
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.assert = dispmix_reset_assert,
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.deassert = dispmix_reset_deassert,
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};
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static int dispmix_reset_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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const struct of_device_id *of_id;
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struct dispmix_reset_controller *drcdev;
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const struct dispmix_reset_pdata *pdata;
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struct resource *res;
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void __iomem *regs;
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struct regmap *regmap;
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struct clk *apb_clk;
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drcdev = devm_kzalloc(dev, sizeof(*drcdev), GFP_KERNEL);
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if (!drcdev)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENODEV;
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regs = devm_ioremap_resource(dev, res);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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apb_clk = devm_clk_get(dev, "disp_apb_root_clk");
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if (IS_ERR(apb_clk)) {
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dev_err(dev, "Unable to get disp apb clock\n");
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return PTR_ERR(apb_clk);
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}
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drcdev->active_low = of_property_read_bool(np, "active_low");
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of_id = of_match_device(dispmix_reset_dt_ids, dev);
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pdata = of_id->data;
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/* init mmio regmap */
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regmap = regmap_init_mmio_clk(NULL, NULL,
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regs, pdata->config);
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if (IS_ERR(regmap)) {
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dev_err(dev, "Failed to init mmio regmap: %ld\n",
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PTR_ERR(regmap));
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return PTR_ERR(regmap);
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}
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drcdev->rstcon = regmap;
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platform_set_drvdata(pdev, drcdev);
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pm_runtime_enable(dev);
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/* register reset controller */
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drcdev->dev = dev;
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drcdev->rcdev.of_node = dev->of_node;
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drcdev->rcdev.owner = THIS_MODULE;
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drcdev->rcdev.nr_resets = pdata->nr_resets;
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drcdev->rcdev.ops = &dispmix_reset_ops;
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return devm_reset_controller_register(dev, &drcdev->rcdev);
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}
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static int dispmix_reset_remove(struct platform_device *pdev)
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{
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pm_runtime_disable(&pdev->dev);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver dispmix_reset_driver = {
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.probe = dispmix_reset_probe,
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.remove = dispmix_reset_remove,
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.driver = {
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.name = DRIVER_NAME,
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.owner = THIS_MODULE,
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.of_match_table = of_match_ptr(dispmix_reset_dt_ids),
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},
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};
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builtin_platform_driver(dispmix_reset_driver);
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MODULE_DESCRIPTION("IMX Display Mix reset driver");
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MODULE_AUTHOR("Fancy Fang <chen.fang@nxp.com>");
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MODULE_LICENSE("GPL");
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