131 lines
4.2 KiB
C
131 lines
4.2 KiB
C
/*
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* deep sleep FSM (finite-state machine) configuration
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*
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* Copyright 2018 NXP
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the above-listed copyright holders nor the
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* names of any contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FSL_SLEEP_FSM_H
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#define _FSL_SLEEP_FSM_H
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#define FSL_STRIDE_4B 4
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#define FSL_STRIDE_8B 8
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/* End flag */
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#define FSM_END_FLAG 0xFFFFFFFFUL
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/* Block offsets */
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#define RCPM_BLOCK_OFFSET 0x00022000
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#define EPU_BLOCK_OFFSET 0x00000000
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#define NPC_BLOCK_OFFSET 0x00001000
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/* EPGCR (Event Processor Global Control Register) */
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#define EPGCR 0x000
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/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
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#define EPEVTCR0 0x050
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#define EPEVTCR9 0x074
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#define EPEVTCR_STRIDE FSL_STRIDE_4B
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/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
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#define EPXTRIGCR 0x090
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/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
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#define EPIMCR0 0x100
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#define EPIMCR31 0x17C
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#define EPIMCR_STRIDE FSL_STRIDE_4B
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/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
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#define EPSMCR0 0x200
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#define EPSMCR15 0x278
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#define EPSMCR_STRIDE FSL_STRIDE_8B
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/* EPECR0-15 (Event Processor Event Control Registers) */
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#define EPECR0 0x300
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#define EPECR15 0x33C
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#define EPECR_STRIDE FSL_STRIDE_4B
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/* EPACR0-15 (Event Processor Action Control Registers) */
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#define EPACR0 0x400
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#define EPACR15 0x43C
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#define EPACR_STRIDE FSL_STRIDE_4B
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/* EPCCRi0-15 (Event Processor Counter Control Registers) */
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#define EPCCR0 0x800
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#define EPCCR15 0x83C
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#define EPCCR31 0x87C
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#define EPCCR_STRIDE FSL_STRIDE_4B
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/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
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#define EPCMPR0 0x900
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#define EPCMPR15 0x93C
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#define EPCMPR31 0x97C
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#define EPCMPR_STRIDE FSL_STRIDE_4B
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/* EPCTR0-31 (Event Processor Counter Register) */
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#define EPCTR0 0xA00
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#define EPCTR31 0xA7C
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#define EPCTR_STRIDE FSL_STRIDE_4B
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/* NPC triggered Memory-Mapped Access Registers */
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#define NCR 0x000
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#define MCCR1 0x0CC
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#define MCSR1 0x0D0
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#define MMAR1LO 0x0D4
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#define MMAR1HI 0x0D8
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#define MMDR1 0x0DC
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#define MCSR2 0x0E0
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#define MMAR2LO 0x0E4
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#define MMAR2HI 0x0E8
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#define MMDR2 0x0EC
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#define MCSR3 0x0F0
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#define MMAR3LO 0x0F4
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#define MMAR3HI 0x0F8
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#define MMDR3 0x0FC
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/* RCPM Core State Action Control Register 0 */
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#define CSTTACR0 0xB00
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/* RCPM Core Group 1 Configuration Register 0 */
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#define CG1CR0 0x31C
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struct fsm_reg_vals {
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u32 offset;
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u32 value;
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};
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void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
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void fsl_epu_setup_default(void __iomem *epu_base);
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void fsl_npc_setup_default(void __iomem *npc_base);
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void fsl_epu_clean_default(void __iomem *epu_base);
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#endif /* _FSL_SLEEP_FSM_H */
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