96 lines
3.4 KiB
C
96 lines
3.4 KiB
C
/* Copyright 2016 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef DPA_SYS_ARM_H
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#define DPA_SYS_ARM_H
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#include <asm/cacheflush.h>
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#include <asm/barrier.h>
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/* Implementation of ARM specific routines */
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/* TODO: NB, we currently assume that hwsync() and lwsync() imply compiler
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* barriers and that dcb*() won't fall victim to compiler or execution
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* reordering with respect to other code/instructions that manipulate the same
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* cacheline. */
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#define hwsync() { asm volatile("dmb st" : : : "memory"); }
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#define lwsync() { asm volatile("dmb st" : : : "memory"); }
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#define dcbf(p) { asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r" (p) : "memory"); }
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#define dcbt_ro(p) { asm volatile("pld [%0, #64];": : "r" (p)); }
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#define dcbt_rw(p) { asm volatile("pldw [%0, #64];": : "r" (p)); }
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#define dcbi(p) { asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r" (p) : "memory"); }
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#define dcbz_64(p) { memset(p, 0, sizeof(*p)); }
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#define dcbf_64(p) \
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do { \
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dcbf((u32)p); \
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} while (0)
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/* Commonly used combo */
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#define dcbit_ro(p) \
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do { \
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dcbi((u32)p); \
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dcbt_ro((u32)p); \
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} while (0)
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static inline u64 mfatb(void)
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{
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return get_cycles();
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}
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static inline u32 in_be32(volatile void *addr)
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{
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return be32_to_cpu(*((volatile u32 *) addr));
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}
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static inline void out_be32(void *addr, u32 val)
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{
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*((u32 *) addr) = cpu_to_be32(val);
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}
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static inline void set_bits(unsigned long mask, volatile unsigned long *p)
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{
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*p |= mask;
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}
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static inline void clear_bits(unsigned long mask, volatile unsigned long *p)
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{
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*p &= ~mask;
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}
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static inline void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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__cpuc_flush_dcache_area((void *) start, stop - start);
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}
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#define hard_smp_processor_id() raw_smp_processor_id()
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#endif
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