202 lines
5.6 KiB
C
202 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#ifndef __INC_HAL8188EPHYREG_H__
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#define __INC_HAL8188EPHYREG_H__
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/*--------------------------Define Parameters-------------------------------*/
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/* */
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/* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */
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/* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */
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/* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */
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/* 3. RF register 0x00-2E */
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/* 4. Bit Mask for BB/RF register */
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/* 5. Other definition for BB/RF R/W */
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/* */
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/* 3. Page8(0x800) */
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#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */
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#define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
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#define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
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#define rFPGA0_XA_HSSIParameter2 0x824
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#define rFPGA0_XB_HSSIParameter1 0x828
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#define rFPGA0_XB_HSSIParameter2 0x82c
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#define rFPGA0_XA_LSSIParameter 0x840
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#define rFPGA0_XB_LSSIParameter 0x844
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#define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
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#define rFPGA0_XCD_SwitchControl 0x85c
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#define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
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#define rFPGA0_XB_RFInterfaceOE 0x864
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#define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */
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#define rFPGA0_XCD_RFInterfaceSW 0x874
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#define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
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#define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
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#define rFPGA0_XB_LSSIReadBack 0x8a4
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#define TransceiverA_HSPI_Readback 0x8b8
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#define TransceiverB_HSPI_Readback 0x8bc
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#define rFPGA0_XAB_RFInterfaceRB 0x8e0
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/* 4. Page9(0x900) */
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/* RF mode & OFDM TxSC RF BW Setting?? */
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#define rFPGA1_RFMOD 0x900
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/* 5. PageA(0xA00) */
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/* Set Control channel to upper or lower - required only for 40MHz */
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#define rCCK0_System 0xa00
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/* */
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/* PageB(0xB00) */
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/* */
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#define rConfig_AntA 0xb68
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#define rConfig_AntB 0xb6c
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/* */
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/* 6. PageC(0xC00) */
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/* */
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#define rOFDM0_TRxPathEnable 0xc04
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#define rOFDM0_TRMuxPar 0xc08
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/* RxIQ DC offset, Rx digital filter, DC notch filter */
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#define rOFDM0_XARxAFE 0xc10
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#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */
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#define rOFDM0_XBRxAFE 0xc18
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#define rOFDM0_XBRxIQImbalance 0xc1c
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#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
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#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
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#define rOFDM0_XAAGCCore1 0xc50 /* DIG */
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#define rOFDM0_XAAGCCore2 0xc54
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#define rOFDM0_XBAGCCore1 0xc58
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#define rOFDM0_XBAGCCore2 0xc5c
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#define rOFDM0_AGCRSSITable 0xc78
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#define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
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#define rOFDM0_XATxAFE 0xc84
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#define rOFDM0_XBTxIQImbalance 0xc88
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#define rOFDM0_XBTxAFE 0xc8c
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#define rOFDM0_XCTxAFE 0xc94
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#define rOFDM0_XDTxAFE 0xc9c
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#define rOFDM0_RxIQExtAnta 0xca0
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/* */
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/* 7. PageD(0xD00) */
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/* */
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#define rOFDM1_LSTF 0xd00
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/* */
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/* 8. PageE(0xE00) */
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/* */
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#define rTxAGC_A_Rate18_06 0xe00
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#define rTxAGC_A_Rate54_24 0xe04
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#define rTxAGC_A_CCK1_Mcs32 0xe08
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#define rTxAGC_A_Mcs03_Mcs00 0xe10
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#define rTxAGC_A_Mcs07_Mcs04 0xe14
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#define rTxAGC_A_Mcs11_Mcs08 0xe18
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#define rTxAGC_A_Mcs15_Mcs12 0xe1c
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#define rTxAGC_B_Rate18_06 0x830
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#define rTxAGC_B_Rate54_24 0x834
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#define rTxAGC_B_CCK1_55_Mcs32 0x838
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#define rTxAGC_B_Mcs03_Mcs00 0x83c
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#define rTxAGC_B_Mcs07_Mcs04 0x848
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#define rTxAGC_B_Mcs11_Mcs08 0x84c
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#define rTxAGC_B_Mcs15_Mcs12 0x868
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#define rTxAGC_B_CCK11_A_CCK2_11 0x86c
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#define rFPGA0_IQK 0xe28
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#define rTx_IQK_Tone_A 0xe30
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#define rRx_IQK_Tone_A 0xe34
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#define rTx_IQK_PI_A 0xe38
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#define rRx_IQK_PI_A 0xe3c
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#define rTx_IQK 0xe40
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#define rRx_IQK 0xe44
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#define rIQK_AGC_Pts 0xe48
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#define rIQK_AGC_Rsp 0xe4c
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#define rIQK_AGC_Cont 0xe60
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#define rBlue_Tooth 0xe6c
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#define rRx_Wait_CCA 0xe70
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#define rTx_CCK_RFON 0xe74
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#define rTx_CCK_BBON 0xe78
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#define rTx_OFDM_RFON 0xe7c
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#define rTx_OFDM_BBON 0xe80
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#define rTx_To_Rx 0xe84
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#define rTx_To_Tx 0xe88
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#define rRx_CCK 0xe8c
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#define rTx_Power_Before_IQK_A 0xe94
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#define rTx_Power_After_IQK_A 0xe9c
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#define rRx_Power_Before_IQK_A_2 0xea4
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#define rRx_Power_After_IQK_A_2 0xeac
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#define rTx_Power_Before_IQK_B 0xeb4
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#define rTx_Power_After_IQK_B 0xebc
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#define rRx_Power_Before_IQK_B_2 0xec4
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#define rRx_Power_After_IQK_B_2 0xecc
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#define rRx_OFDM 0xed0
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#define rRx_Wait_RIFS 0xed4
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#define rRx_TO_Rx 0xed8
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#define rStandby 0xedc
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#define rSleep 0xee0
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#define rPMPD_ANAEN 0xeec
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/* */
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/* RL6052 Register definition */
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/* */
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#define RF_AC 0x00 /* */
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#define RF_CHNLBW 0x18 /* RF channel and BW switch */
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#define RF_T_METER_88E 0x42 /* */
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#define RF_RCK_OS 0x30 /* RF TX PA control */
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#define RF_TXPA_G1 0x31 /* RF TX PA control */
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#define RF_TXPA_G2 0x32 /* RF TX PA control */
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#define RF_WE_LUT 0xEF
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/* */
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/* Bit Mask */
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/* */
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/* 2. Page8(0x800) */
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#define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
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#define bCCKEn 0x1000000
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#define bOFDMEn 0x2000000
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#define bLSSIReadAddress 0x7f800000 /* T65 RF */
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#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
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#define bLSSIReadBackData 0xfffff /* T65 RF */
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#define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 */
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/* */
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/* Other Definition */
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/* */
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/* for PutRegsetting & GetRegSetting BitMask */
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#define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
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#define bMaskByte1 0xff00
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#define bMaskByte3 0xff000000
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#define bMaskDWord 0xffffffff
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#define bMask12Bits 0xfff
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#define bMaskOFDM_D 0xffc00000
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/* for PutRFRegsetting & GetRFRegSetting BitMask */
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#define bRFRegOffsetMask 0xfffff
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#endif
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