91 lines
2.8 KiB
C
91 lines
2.8 KiB
C
/*
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* ak4497.h -- audio driver for ak4497
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*
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* Copyright (C) 2016 Asahi Kasei Microdevices Corporation
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* Copyright (C) 2017, NXP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef _RPMSG_AK4497_H
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#define _RPMSG_AK4497_H
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#define AK4497_00_CONTROL1 0x00
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#define AK4497_01_CONTROL2 0x01
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#define AK4497_02_CONTROL3 0x02
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#define AK4497_03_LCHATT 0x03
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#define AK4497_04_RCHATT 0x04
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#define AK4497_05_CONTROL4 0x05
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#define AK4497_06_DSD1 0x06
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#define AK4497_07_CONTROL5 0x07
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#define AK4497_08_SOUNDCONTROL 0x08
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#define AK4497_09_DSD2 0x09
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#define AK4497_0A_CONTROL7 0x0A
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#define AK4497_0B_CONTROL8 0x0B
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#define AK4497_0C_RESERVED 0x0C
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#define AK4497_0D_RESERVED 0x0D
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#define AK4497_0E_RESERVED 0x0E
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#define AK4497_0F_RESERVED 0x0F
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#define AK4497_10_RESERVED 0x10
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#define AK4497_11_RESERVED 0x11
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#define AK4497_12_RESERVED 0x12
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#define AK4497_13_RESERVED 0x13
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#define AK4497_14_RESERVED 0x14
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#define AK4497_15_DFSREAD 0x15
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#define AK4497_MAX_REGISTERS (AK4497_15_DFSREAD)
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/* Bitfield Definitions */
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/* AK4497_00_CONTROL1 (0x00) Fields */
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#define AK4497_DIF 0x0E
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#define AK4497_DIF_MSB_MODE (2 << 1)
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#define AK4497_DIF_I2S_MODE (3 << 1)
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#define AK4497_DIF_32BIT_MODE (4 << 1)
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#define AK4497_DIF_16BIT_LSB (0 << 1)
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#define AK4497_DIF_20BIT_LSB (1 << 1)
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#define AK4497_DIF_24BIT_MSB (2 << 1)
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#define AK4497_DIF_24BIT_I2S (3 << 1)
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#define AK4497_DIF_24BIT_LSB (4 << 1)
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#define AK4497_DIF_32BIT_LSB (5 << 1)
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#define AK4497_DIF_32BIT_MSB (6 << 1)
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#define AK4497_DIF_32BIT_I2S (7 << 1)
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/* AK4497_02_CONTROL3 (0x02) Fields */
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#define AK4497_DIF_DSD 0x80
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#define AK4497_DIF_DSD_MODE (1 << 7)
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/* AK4497_01_CONTROL2 (0x01) Fields */
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/* AK4497_05_CONTROL4 (0x05) Fields */
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#define AK4497_DFS 0x18
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#define AK4497_DFS_48KHZ (0x0 << 3) // 30kHz to 54kHz
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#define AK4497_DFS_96KHZ (0x1 << 3) // 54kHz to 108kHz
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#define AK4497_DFS_192KHZ (0x2 << 3) // 120kHz to 216kHz
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#define AK4497_DFS_384KHZ (0x0 << 3)
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#define AK4497_DFS_768KHZ (0x1 << 3)
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#define AK4497_DFS2 0x2
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#define AK4497_DFS2_48KHZ (0x0 << 1) // 30kHz to 216kHz
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#define AK4497_DFS2_384KHZ (0x1 << 1) // 384kHz, 768kHz to 108kHz
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#define AK4497_DSDSEL0 0x1
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#define AK4497_DSDSEL0_2MHZ 0x0
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#define AK4497_DSDSEL0_5MHZ 0x1
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#define AK4497_DSDSEL0_11MHZ 0x0
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#define AK4497_DSDSEL0_22MHZ 0x1
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#define AK4497_DSDSEL1 0x1
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#define AK4497_DSDSEL1_2MHZ 0x0
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#define AK4497_DSDSEL1_5MHZ 0x0
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#define AK4497_DSDSEL1_11MHZ 0x1
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#define AK4497_DSDSEL1_22MHZ 0x1
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#endif
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