50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 NXP
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*/
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#ifndef _FSL_AUD2HTX_H
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#define _FSL_AUD2HTX_H
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#define FSL_AUD2HTX_FORMATS (SNDRV_PCM_FMTBIT_S24_LE)
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#define AUD2HTX_CTRL 0x0
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#define AUD2HTX_CTRL_EXT 0x4
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#define AUD2HTX_WR 0x8
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#define AUD2HTX_STATUS 0xC
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#define AUD2HTX_IRQ_NOMASK 0x10
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#define AUD2HTX_IRQ_MASKED 0x14
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#define AUD2HTX_IRQ_MASK 0x18
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#define AUD2HTX_CTRL_EN BIT(0)
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#define AUD2HTX_CTRE_DE BIT(0)
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#define AUD2HTX_CTRE_DT_SHIFT 0x1
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#define AUD2HTX_CTRE_DT_WIDTH 0x2
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#define AUD2HTX_CTRE_DT_MASK ((BIT(AUD2HTX_CTRE_DT_WIDTH) - 1) \
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<< AUD2HTX_CTRE_DT_SHIFT)
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#define AUD2HTX_CTRE_WL_SHIFT 16
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#define AUD2HTX_CTRE_WL_WIDTH 5
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#define AUD2HTX_CTRE_WL_MASK ((BIT(AUD2HTX_CTRE_WL_WIDTH) - 1) \
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<< AUD2HTX_CTRE_WL_SHIFT)
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#define AUD2HTX_CTRE_WH_SHIFT 24
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#define AUD2HTX_CTRE_WH_WIDTH 5
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#define AUD2HTX_CTRE_WH_MASK ((BIT(AUD2HTX_CTRE_WH_WIDTH) - 1) \
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<< AUD2HTX_CTRE_WH_SHIFT)
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#define AUD2HTX_WM_HIGH_IRQ_MASK BIT(2)
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#define AUD2HTX_WM_LOW_IRQ_MASK BIT(1)
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#define AUD2HTX_OVF_MASK BIT(0)
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struct fsl_aud2htx {
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struct platform_device *pdev;
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struct regmap *regmap;
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struct clk *bus_clk;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct snd_dmaengine_dai_dma_data dma_params_tx;
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};
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#endif /* _FSL_AUD2HTX_H */
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