![Alan Cox](/assets/img/avatar_default.png)
This allows parallel scan and the like to be set without having to stop using the existing full helper functions. This patch merely adds the argument and fixes up the callers. It doesn't undo the special cases already in the tree or add any new parallel callers. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
290 lines
7.4 KiB
C
290 lines
7.4 KiB
C
/*
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* pata_oldpiix.c - Intel PATA/SATA controllers
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*
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* (C) 2005 Red Hat
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*
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* Some parts based on ata_piix.c by Jeff Garzik and others.
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*
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* Early PIIX differs significantly from the later PIIX as it lacks
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* SITRE and the slave timing registers. This means that you have to
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* set timing per channel, or be clever. Libata tells us whenever it
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* does drive selection and we use this to reload the timings.
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*
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* Because of these behaviour differences PIIX gets its own driver module.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/ata.h>
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#define DRV_NAME "pata_oldpiix"
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#define DRV_VERSION "0.5.5"
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/**
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* oldpiix_pre_reset - probe begin
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* @link: ATA link
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* @deadline: deadline jiffies for the operation
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*
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* Set up cable type and use generic probe init
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*/
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static int oldpiix_pre_reset(struct ata_link *link, unsigned long deadline)
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{
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struct ata_port *ap = link->ap;
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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static const struct pci_bits oldpiix_enable_bits[] = {
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{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
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{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
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};
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if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_sff_prereset(link, deadline);
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}
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/**
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* oldpiix_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: Device whose timings we are configuring
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*
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* Set PIO mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
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u16 idetm_data;
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int control = 0;
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/*
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* See Intel Document 298600-004 for the timing programing rules
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* for PIIX/ICH. Note that the early PIIX does not have the slave
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* timing port at 0x44.
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*/
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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if (pio > 1)
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control |= 1; /* TIME */
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if (ata_pio_need_iordy(adev))
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control |= 2; /* IE */
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/* Intel specifies that the prefetch/posting is for disk only */
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if (adev->class == ATA_DEV_ATA)
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control |= 4; /* PPE */
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pci_read_config_word(dev, idetm_port, &idetm_data);
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/*
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* Set PPE, IE and TIME as appropriate.
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* Clear the other drive's timing bits.
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*/
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if (adev->devno == 0) {
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idetm_data &= 0xCCE0;
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idetm_data |= control;
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} else {
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idetm_data &= 0xCC0E;
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idetm_data |= (control << 4);
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}
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idetm_data |= (timings[pio][0] << 12) |
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(timings[pio][1] << 8);
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pci_write_config_word(dev, idetm_port, idetm_data);
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/* Track which port is configured */
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ap->private_data = adev;
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}
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/**
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* oldpiix_set_dmamode - Initialize host controller PATA DMA timings
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* @ap: Port whose timings we are configuring
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* @adev: Device to program
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*
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* Set MWDMA mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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u8 idetm_port = ap->port_no ? 0x42 : 0x40;
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u16 idetm_data;
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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/*
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* MWDMA is driven by the PIO timings. We must also enable
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* IORDY unconditionally along with TIME1. PPE has already
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* been set when the PIO timing was set.
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*/
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unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
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unsigned int control;
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const unsigned int needed_pio[3] = {
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XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
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};
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int pio = needed_pio[mwdma] - XFER_PIO_0;
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pci_read_config_word(dev, idetm_port, &idetm_data);
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control = 3; /* IORDY|TIME0 */
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/* Intel specifies that the PPE functionality is for disk only */
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if (adev->class == ATA_DEV_ATA)
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control |= 4; /* PPE enable */
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/* If the drive MWDMA is faster than it can do PIO then
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we must force PIO into PIO0 */
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if (adev->pio_mode < needed_pio[mwdma])
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/* Enable DMA timing only */
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control |= 8; /* PIO cycles in PIO0 */
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/* Mask out the relevant control and timing bits we will load. Also
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clear the other drive TIME register as a precaution */
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if (adev->devno == 0) {
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idetm_data &= 0xCCE0;
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idetm_data |= control;
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} else {
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idetm_data &= 0xCC0E;
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idetm_data |= (control << 4);
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}
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idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
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pci_write_config_word(dev, idetm_port, idetm_data);
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/* Track which port is configured */
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ap->private_data = adev;
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}
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/**
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* oldpiix_qc_issue - command issue
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* @qc: command pending
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*
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* Called when the libata layer is about to issue a command. We wrap
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* this interface so that we can load the correct ATA timings if
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* necessary. Our logic also clears TIME0/TIME1 for the other device so
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* that, even if we get this wrong, cycles to the other device will
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* be made PIO0.
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*/
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static unsigned int oldpiix_qc_issue(struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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struct ata_device *adev = qc->dev;
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if (adev != ap->private_data) {
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oldpiix_set_piomode(ap, adev);
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if (ata_dma_enabled(adev))
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oldpiix_set_dmamode(ap, adev);
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}
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return ata_sff_qc_issue(qc);
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}
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static struct scsi_host_template oldpiix_sht = {
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ATA_BMDMA_SHT(DRV_NAME),
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};
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static struct ata_port_operations oldpiix_pata_ops = {
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.inherits = &ata_bmdma_port_ops,
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.qc_issue = oldpiix_qc_issue,
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.cable_detect = ata_cable_40wire,
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.set_piomode = oldpiix_set_piomode,
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.set_dmamode = oldpiix_set_dmamode,
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.prereset = oldpiix_pre_reset,
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};
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/**
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* oldpiix_init_one - Register PIIX ATA PCI device with kernel services
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* @pdev: PCI device to register
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* @ent: Entry in oldpiix_pci_tbl matching with @pdev
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*
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* Called from kernel PCI layer. We probe for combined mode (sigh),
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* and then hand over control to libata, for it to do the rest.
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*
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* LOCKING:
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* Inherited from PCI layer (may sleep).
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*
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* RETURNS:
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* Zero on success, or -ERRNO value.
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*/
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static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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static const struct ata_port_info info = {
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.flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA12_ONLY,
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.port_ops = &oldpiix_pata_ops,
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};
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const struct ata_port_info *ppi[] = { &info, NULL };
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev,
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"version " DRV_VERSION "\n");
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return ata_pci_sff_init_one(pdev, ppi, &oldpiix_sht, NULL, 0);
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}
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static const struct pci_device_id oldpiix_pci_tbl[] = {
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{ PCI_VDEVICE(INTEL, 0x1230), },
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{ } /* terminate list */
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};
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static struct pci_driver oldpiix_pci_driver = {
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.name = DRV_NAME,
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.id_table = oldpiix_pci_tbl,
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.probe = oldpiix_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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};
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static int __init oldpiix_init(void)
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{
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return pci_register_driver(&oldpiix_pci_driver);
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}
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static void __exit oldpiix_exit(void)
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{
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pci_unregister_driver(&oldpiix_pci_driver);
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}
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module_init(oldpiix_init);
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module_exit(oldpiix_exit);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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