![Linus Torvalds](/assets/img/avatar_default.png)
Artem's cleanup of the MTD API continues apace. Fixes and improvements for ST FSMC and SuperH FLCTL NAND, amongst others. More work on DiskOnChip G3, new driver for DiskOnChip G4. Clean up debug/warning printks in JFFS2 to use pr_<level>. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iEYEABECAAYFAk92K6UACgkQdwG7hYl686NrMACfWQJRWasR78MWKfkT2vWZwTFJ X5AAoKiSYO2pfo5gWJGOAahNC1zUqMX0 =i3Vb -----END PGP SIGNATURE----- Merge tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6 Pull MTD changes from David Woodhouse: - Artem's cleanup of the MTD API continues apace. - Fixes and improvements for ST FSMC and SuperH FLCTL NAND, amongst others. - More work on DiskOnChip G3, new driver for DiskOnChip G4. - Clean up debug/warning printks in JFFS2 to use pr_<level>. Fix up various trivial conflicts, largely due to changes in calling conventions for things like dmaengine_prep_slave_sg() (new inline wrapper to hide new parameter, clashing with rewrite of previously last parameter that used to be an 'append' flag, and is now a bitmap of 'unsigned long flags'). (Also some header file fallout - like so many merges this merge window - and silly conflicts with sparse fixes) * tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6: (120 commits) mtd: docg3 add protection against concurrency mtd: docg3 refactor cascade floors structure mtd: docg3 increase write/erase timeout mtd: docg3 fix inbound calculations mtd: nand: gpmi: fix function annotations mtd: phram: fix section mismatch for phram_setup mtd: unify initialization of erase_info->fail_addr mtd: support ONFI multi lun NAND mtd: sm_ftl: fix typo in major number. mtd: add device-tree support to spear_smi mtd: spear_smi: Remove default partition information from driver mtd: Add device-tree support to fsmc_nand mtd: fix section mismatch for doc_probe_device mtd: nand/fsmc: Remove sparse warnings and errors mtd: nand/fsmc: Add DMA support mtd: nand/fsmc: Access the NAND device word by word whenever possible mtd: nand/fsmc: Use dev_err to report error scenario mtd: nand/fsmc: Use devm routines mtd: nand/fsmc: Modify fsmc driver to accept nand timing parameters via platform mtd: fsmc_nand: add pm callbacks to support hibernation ...
720 lines
18 KiB
C
720 lines
18 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* Refer to drivers/dma/imx-sdma.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/clk.h>
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#include <linux/wait.h>
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#include <linux/sched.h>
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#include <linux/semaphore.h>
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/dmaengine.h>
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#include <linux/delay.h>
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#include <linux/fsl/mxs-dma.h>
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#include <asm/irq.h>
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#include <mach/mxs.h>
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#include <mach/common.h>
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#include "dmaengine.h"
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/*
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* NOTE: The term "PIO" throughout the mxs-dma implementation means
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* PIO mode of mxs apbh-dma and apbx-dma. With this working mode,
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* dma can program the controller registers of peripheral devices.
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*/
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#define MXS_DMA_APBH 0
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#define MXS_DMA_APBX 1
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#define dma_is_apbh() (mxs_dma->dev_id == MXS_DMA_APBH)
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#define APBH_VERSION_LATEST 3
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#define apbh_is_old() (mxs_dma->version < APBH_VERSION_LATEST)
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#define HW_APBHX_CTRL0 0x000
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#define BM_APBH_CTRL0_APB_BURST8_EN (1 << 29)
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#define BM_APBH_CTRL0_APB_BURST_EN (1 << 28)
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#define BP_APBH_CTRL0_RESET_CHANNEL 16
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#define HW_APBHX_CTRL1 0x010
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#define HW_APBHX_CTRL2 0x020
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#define HW_APBHX_CHANNEL_CTRL 0x030
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#define BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL 16
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#define HW_APBH_VERSION (cpu_is_mx23() ? 0x3f0 : 0x800)
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#define HW_APBX_VERSION 0x800
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#define BP_APBHX_VERSION_MAJOR 24
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#define HW_APBHX_CHn_NXTCMDAR(n) \
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(((dma_is_apbh() && apbh_is_old()) ? 0x050 : 0x110) + (n) * 0x70)
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#define HW_APBHX_CHn_SEMA(n) \
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(((dma_is_apbh() && apbh_is_old()) ? 0x080 : 0x140) + (n) * 0x70)
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/*
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* ccw bits definitions
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*
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* COMMAND: 0..1 (2)
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* CHAIN: 2 (1)
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* IRQ: 3 (1)
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* NAND_LOCK: 4 (1) - not implemented
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* NAND_WAIT4READY: 5 (1) - not implemented
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* DEC_SEM: 6 (1)
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* WAIT4END: 7 (1)
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* HALT_ON_TERMINATE: 8 (1)
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* TERMINATE_FLUSH: 9 (1)
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* RESERVED: 10..11 (2)
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* PIO_NUM: 12..15 (4)
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*/
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#define BP_CCW_COMMAND 0
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#define BM_CCW_COMMAND (3 << 0)
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#define CCW_CHAIN (1 << 2)
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#define CCW_IRQ (1 << 3)
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#define CCW_DEC_SEM (1 << 6)
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#define CCW_WAIT4END (1 << 7)
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#define CCW_HALT_ON_TERM (1 << 8)
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#define CCW_TERM_FLUSH (1 << 9)
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#define BP_CCW_PIO_NUM 12
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#define BM_CCW_PIO_NUM (0xf << 12)
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#define BF_CCW(value, field) (((value) << BP_CCW_##field) & BM_CCW_##field)
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#define MXS_DMA_CMD_NO_XFER 0
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#define MXS_DMA_CMD_WRITE 1
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#define MXS_DMA_CMD_READ 2
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#define MXS_DMA_CMD_DMA_SENSE 3 /* not implemented */
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struct mxs_dma_ccw {
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u32 next;
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u16 bits;
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u16 xfer_bytes;
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#define MAX_XFER_BYTES 0xff00
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u32 bufaddr;
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#define MXS_PIO_WORDS 16
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u32 pio_words[MXS_PIO_WORDS];
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};
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#define NUM_CCW (int)(PAGE_SIZE / sizeof(struct mxs_dma_ccw))
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struct mxs_dma_chan {
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struct mxs_dma_engine *mxs_dma;
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struct dma_chan chan;
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struct dma_async_tx_descriptor desc;
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struct tasklet_struct tasklet;
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int chan_irq;
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struct mxs_dma_ccw *ccw;
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dma_addr_t ccw_phys;
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int desc_count;
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enum dma_status status;
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unsigned int flags;
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#define MXS_DMA_SG_LOOP (1 << 0)
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};
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#define MXS_DMA_CHANNELS 16
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#define MXS_DMA_CHANNELS_MASK 0xffff
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struct mxs_dma_engine {
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int dev_id;
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unsigned int version;
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void __iomem *base;
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struct clk *clk;
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struct dma_device dma_device;
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struct device_dma_parameters dma_parms;
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struct mxs_dma_chan mxs_chans[MXS_DMA_CHANNELS];
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};
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static void mxs_dma_reset_chan(struct mxs_dma_chan *mxs_chan)
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{
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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int chan_id = mxs_chan->chan.chan_id;
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if (dma_is_apbh() && apbh_is_old())
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writel(1 << (chan_id + BP_APBH_CTRL0_RESET_CHANNEL),
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mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
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else
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writel(1 << (chan_id + BP_APBHX_CHANNEL_CTRL_RESET_CHANNEL),
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
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}
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static void mxs_dma_enable_chan(struct mxs_dma_chan *mxs_chan)
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{
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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int chan_id = mxs_chan->chan.chan_id;
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/* set cmd_addr up */
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writel(mxs_chan->ccw_phys,
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mxs_dma->base + HW_APBHX_CHn_NXTCMDAR(chan_id));
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/* write 1 to SEMA to kick off the channel */
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writel(1, mxs_dma->base + HW_APBHX_CHn_SEMA(chan_id));
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}
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static void mxs_dma_disable_chan(struct mxs_dma_chan *mxs_chan)
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{
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mxs_chan->status = DMA_SUCCESS;
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}
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static void mxs_dma_pause_chan(struct mxs_dma_chan *mxs_chan)
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{
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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int chan_id = mxs_chan->chan.chan_id;
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/* freeze the channel */
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if (dma_is_apbh() && apbh_is_old())
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
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else
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_SET_ADDR);
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mxs_chan->status = DMA_PAUSED;
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}
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static void mxs_dma_resume_chan(struct mxs_dma_chan *mxs_chan)
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{
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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int chan_id = mxs_chan->chan.chan_id;
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/* unfreeze the channel */
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if (dma_is_apbh() && apbh_is_old())
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CTRL0 + MXS_CLR_ADDR);
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else
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writel(1 << chan_id,
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mxs_dma->base + HW_APBHX_CHANNEL_CTRL + MXS_CLR_ADDR);
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mxs_chan->status = DMA_IN_PROGRESS;
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}
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static struct mxs_dma_chan *to_mxs_dma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct mxs_dma_chan, chan);
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}
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static dma_cookie_t mxs_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(tx->chan);
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mxs_dma_enable_chan(mxs_chan);
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return dma_cookie_assign(tx);
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}
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static void mxs_dma_tasklet(unsigned long data)
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{
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struct mxs_dma_chan *mxs_chan = (struct mxs_dma_chan *) data;
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if (mxs_chan->desc.callback)
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mxs_chan->desc.callback(mxs_chan->desc.callback_param);
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}
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static irqreturn_t mxs_dma_int_handler(int irq, void *dev_id)
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{
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struct mxs_dma_engine *mxs_dma = dev_id;
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u32 stat1, stat2;
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/* completion status */
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stat1 = readl(mxs_dma->base + HW_APBHX_CTRL1);
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stat1 &= MXS_DMA_CHANNELS_MASK;
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writel(stat1, mxs_dma->base + HW_APBHX_CTRL1 + MXS_CLR_ADDR);
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/* error status */
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stat2 = readl(mxs_dma->base + HW_APBHX_CTRL2);
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writel(stat2, mxs_dma->base + HW_APBHX_CTRL2 + MXS_CLR_ADDR);
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/*
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* When both completion and error of termination bits set at the
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* same time, we do not take it as an error. IOW, it only becomes
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* an error we need to handle here in case of either it's (1) a bus
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* error or (2) a termination error with no completion.
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*/
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stat2 = ((stat2 >> MXS_DMA_CHANNELS) & stat2) | /* (1) */
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(~(stat2 >> MXS_DMA_CHANNELS) & stat2 & ~stat1); /* (2) */
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/* combine error and completion status for checking */
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stat1 = (stat2 << MXS_DMA_CHANNELS) | stat1;
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while (stat1) {
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int channel = fls(stat1) - 1;
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struct mxs_dma_chan *mxs_chan =
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&mxs_dma->mxs_chans[channel % MXS_DMA_CHANNELS];
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if (channel >= MXS_DMA_CHANNELS) {
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dev_dbg(mxs_dma->dma_device.dev,
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"%s: error in channel %d\n", __func__,
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channel - MXS_DMA_CHANNELS);
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mxs_chan->status = DMA_ERROR;
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mxs_dma_reset_chan(mxs_chan);
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} else {
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if (mxs_chan->flags & MXS_DMA_SG_LOOP)
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mxs_chan->status = DMA_IN_PROGRESS;
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else
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mxs_chan->status = DMA_SUCCESS;
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}
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stat1 &= ~(1 << channel);
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if (mxs_chan->status == DMA_SUCCESS)
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dma_cookie_complete(&mxs_chan->desc);
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/* schedule tasklet on this channel */
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tasklet_schedule(&mxs_chan->tasklet);
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}
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return IRQ_HANDLED;
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}
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static int mxs_dma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
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struct mxs_dma_data *data = chan->private;
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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int ret;
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if (!data)
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return -EINVAL;
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mxs_chan->chan_irq = data->chan_irq;
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mxs_chan->ccw = dma_alloc_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
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&mxs_chan->ccw_phys, GFP_KERNEL);
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if (!mxs_chan->ccw) {
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ret = -ENOMEM;
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goto err_alloc;
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}
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memset(mxs_chan->ccw, 0, PAGE_SIZE);
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if (mxs_chan->chan_irq != NO_IRQ) {
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ret = request_irq(mxs_chan->chan_irq, mxs_dma_int_handler,
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0, "mxs-dma", mxs_dma);
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if (ret)
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goto err_irq;
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}
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ret = clk_prepare_enable(mxs_dma->clk);
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if (ret)
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goto err_clk;
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mxs_dma_reset_chan(mxs_chan);
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dma_async_tx_descriptor_init(&mxs_chan->desc, chan);
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mxs_chan->desc.tx_submit = mxs_dma_tx_submit;
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/* the descriptor is ready */
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async_tx_ack(&mxs_chan->desc);
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return 0;
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err_clk:
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free_irq(mxs_chan->chan_irq, mxs_dma);
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err_irq:
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dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
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mxs_chan->ccw, mxs_chan->ccw_phys);
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err_alloc:
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return ret;
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}
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static void mxs_dma_free_chan_resources(struct dma_chan *chan)
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{
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struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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mxs_dma_disable_chan(mxs_chan);
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free_irq(mxs_chan->chan_irq, mxs_dma);
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dma_free_coherent(mxs_dma->dma_device.dev, PAGE_SIZE,
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mxs_chan->ccw, mxs_chan->ccw_phys);
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clk_disable_unprepare(mxs_dma->clk);
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}
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/*
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* How to use the flags for ->device_prep_slave_sg() :
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* [1] If there is only one DMA command in the DMA chain, the code should be:
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* ......
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* ->device_prep_slave_sg(DMA_CTRL_ACK);
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* ......
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* [2] If there are two DMA commands in the DMA chain, the code should be
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* ......
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* ->device_prep_slave_sg(0);
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* ......
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* ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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* ......
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* [3] If there are more than two DMA commands in the DMA chain, the code
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* should be:
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* ......
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* ->device_prep_slave_sg(0); // First
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* ......
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* ->device_prep_slave_sg(DMA_PREP_INTERRUPT [| DMA_CTRL_ACK]);
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* ......
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* ->device_prep_slave_sg(DMA_PREP_INTERRUPT | DMA_CTRL_ACK); // Last
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* ......
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*/
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static struct dma_async_tx_descriptor *mxs_dma_prep_slave_sg(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags, void *context)
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{
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struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
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struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
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struct mxs_dma_ccw *ccw;
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struct scatterlist *sg;
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int i, j;
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u32 *pio;
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bool append = flags & DMA_PREP_INTERRUPT;
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int idx = append ? mxs_chan->desc_count : 0;
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if (mxs_chan->status == DMA_IN_PROGRESS && !append)
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return NULL;
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if (sg_len + (append ? idx : 0) > NUM_CCW) {
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dev_err(mxs_dma->dma_device.dev,
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"maximum number of sg exceeded: %d > %d\n",
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sg_len, NUM_CCW);
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goto err_out;
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}
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mxs_chan->status = DMA_IN_PROGRESS;
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mxs_chan->flags = 0;
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/*
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* If the sg is prepared with append flag set, the sg
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* will be appended to the last prepared sg.
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*/
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if (append) {
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BUG_ON(idx < 1);
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ccw = &mxs_chan->ccw[idx - 1];
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ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
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ccw->bits |= CCW_CHAIN;
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ccw->bits &= ~CCW_IRQ;
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ccw->bits &= ~CCW_DEC_SEM;
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} else {
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idx = 0;
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}
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if (direction == DMA_TRANS_NONE) {
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ccw = &mxs_chan->ccw[idx++];
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pio = (u32 *) sgl;
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for (j = 0; j < sg_len;)
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ccw->pio_words[j++] = *pio++;
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ccw->bits = 0;
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ccw->bits |= CCW_IRQ;
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ccw->bits |= CCW_DEC_SEM;
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if (flags & DMA_CTRL_ACK)
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ccw->bits |= CCW_WAIT4END;
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ccw->bits |= CCW_HALT_ON_TERM;
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ccw->bits |= CCW_TERM_FLUSH;
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ccw->bits |= BF_CCW(sg_len, PIO_NUM);
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ccw->bits |= BF_CCW(MXS_DMA_CMD_NO_XFER, COMMAND);
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} else {
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for_each_sg(sgl, sg, sg_len, i) {
|
|
if (sg->length > MAX_XFER_BYTES) {
|
|
dev_err(mxs_dma->dma_device.dev, "maximum bytes for sg entry exceeded: %d > %d\n",
|
|
sg->length, MAX_XFER_BYTES);
|
|
goto err_out;
|
|
}
|
|
|
|
ccw = &mxs_chan->ccw[idx++];
|
|
|
|
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * idx;
|
|
ccw->bufaddr = sg->dma_address;
|
|
ccw->xfer_bytes = sg->length;
|
|
|
|
ccw->bits = 0;
|
|
ccw->bits |= CCW_CHAIN;
|
|
ccw->bits |= CCW_HALT_ON_TERM;
|
|
ccw->bits |= CCW_TERM_FLUSH;
|
|
ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
|
|
MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ,
|
|
COMMAND);
|
|
|
|
if (i + 1 == sg_len) {
|
|
ccw->bits &= ~CCW_CHAIN;
|
|
ccw->bits |= CCW_IRQ;
|
|
ccw->bits |= CCW_DEC_SEM;
|
|
if (flags & DMA_CTRL_ACK)
|
|
ccw->bits |= CCW_WAIT4END;
|
|
}
|
|
}
|
|
}
|
|
mxs_chan->desc_count = idx;
|
|
|
|
return &mxs_chan->desc;
|
|
|
|
err_out:
|
|
mxs_chan->status = DMA_ERROR;
|
|
return NULL;
|
|
}
|
|
|
|
static struct dma_async_tx_descriptor *mxs_dma_prep_dma_cyclic(
|
|
struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
|
|
size_t period_len, enum dma_transfer_direction direction,
|
|
void *context)
|
|
{
|
|
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
|
struct mxs_dma_engine *mxs_dma = mxs_chan->mxs_dma;
|
|
int num_periods = buf_len / period_len;
|
|
int i = 0, buf = 0;
|
|
|
|
if (mxs_chan->status == DMA_IN_PROGRESS)
|
|
return NULL;
|
|
|
|
mxs_chan->status = DMA_IN_PROGRESS;
|
|
mxs_chan->flags |= MXS_DMA_SG_LOOP;
|
|
|
|
if (num_periods > NUM_CCW) {
|
|
dev_err(mxs_dma->dma_device.dev,
|
|
"maximum number of sg exceeded: %d > %d\n",
|
|
num_periods, NUM_CCW);
|
|
goto err_out;
|
|
}
|
|
|
|
if (period_len > MAX_XFER_BYTES) {
|
|
dev_err(mxs_dma->dma_device.dev,
|
|
"maximum period size exceeded: %d > %d\n",
|
|
period_len, MAX_XFER_BYTES);
|
|
goto err_out;
|
|
}
|
|
|
|
while (buf < buf_len) {
|
|
struct mxs_dma_ccw *ccw = &mxs_chan->ccw[i];
|
|
|
|
if (i + 1 == num_periods)
|
|
ccw->next = mxs_chan->ccw_phys;
|
|
else
|
|
ccw->next = mxs_chan->ccw_phys + sizeof(*ccw) * (i + 1);
|
|
|
|
ccw->bufaddr = dma_addr;
|
|
ccw->xfer_bytes = period_len;
|
|
|
|
ccw->bits = 0;
|
|
ccw->bits |= CCW_CHAIN;
|
|
ccw->bits |= CCW_IRQ;
|
|
ccw->bits |= CCW_HALT_ON_TERM;
|
|
ccw->bits |= CCW_TERM_FLUSH;
|
|
ccw->bits |= BF_CCW(direction == DMA_DEV_TO_MEM ?
|
|
MXS_DMA_CMD_WRITE : MXS_DMA_CMD_READ, COMMAND);
|
|
|
|
dma_addr += period_len;
|
|
buf += period_len;
|
|
|
|
i++;
|
|
}
|
|
mxs_chan->desc_count = i;
|
|
|
|
return &mxs_chan->desc;
|
|
|
|
err_out:
|
|
mxs_chan->status = DMA_ERROR;
|
|
return NULL;
|
|
}
|
|
|
|
static int mxs_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
|
|
unsigned long arg)
|
|
{
|
|
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
|
int ret = 0;
|
|
|
|
switch (cmd) {
|
|
case DMA_TERMINATE_ALL:
|
|
mxs_dma_reset_chan(mxs_chan);
|
|
mxs_dma_disable_chan(mxs_chan);
|
|
break;
|
|
case DMA_PAUSE:
|
|
mxs_dma_pause_chan(mxs_chan);
|
|
break;
|
|
case DMA_RESUME:
|
|
mxs_dma_resume_chan(mxs_chan);
|
|
break;
|
|
default:
|
|
ret = -ENOSYS;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static enum dma_status mxs_dma_tx_status(struct dma_chan *chan,
|
|
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
|
{
|
|
struct mxs_dma_chan *mxs_chan = to_mxs_dma_chan(chan);
|
|
dma_cookie_t last_used;
|
|
|
|
last_used = chan->cookie;
|
|
dma_set_tx_state(txstate, chan->completed_cookie, last_used, 0);
|
|
|
|
return mxs_chan->status;
|
|
}
|
|
|
|
static void mxs_dma_issue_pending(struct dma_chan *chan)
|
|
{
|
|
/*
|
|
* Nothing to do. We only have a single descriptor.
|
|
*/
|
|
}
|
|
|
|
static int __init mxs_dma_init(struct mxs_dma_engine *mxs_dma)
|
|
{
|
|
int ret;
|
|
|
|
ret = clk_prepare_enable(mxs_dma->clk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = mxs_reset_block(mxs_dma->base);
|
|
if (ret)
|
|
goto err_out;
|
|
|
|
/* only major version matters */
|
|
mxs_dma->version = readl(mxs_dma->base +
|
|
((mxs_dma->dev_id == MXS_DMA_APBX) ?
|
|
HW_APBX_VERSION : HW_APBH_VERSION)) >>
|
|
BP_APBHX_VERSION_MAJOR;
|
|
|
|
/* enable apbh burst */
|
|
if (dma_is_apbh()) {
|
|
writel(BM_APBH_CTRL0_APB_BURST_EN,
|
|
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
|
|
writel(BM_APBH_CTRL0_APB_BURST8_EN,
|
|
mxs_dma->base + HW_APBHX_CTRL0 + MXS_SET_ADDR);
|
|
}
|
|
|
|
/* enable irq for all the channels */
|
|
writel(MXS_DMA_CHANNELS_MASK << MXS_DMA_CHANNELS,
|
|
mxs_dma->base + HW_APBHX_CTRL1 + MXS_SET_ADDR);
|
|
|
|
err_out:
|
|
clk_disable_unprepare(mxs_dma->clk);
|
|
return ret;
|
|
}
|
|
|
|
static int __init mxs_dma_probe(struct platform_device *pdev)
|
|
{
|
|
const struct platform_device_id *id_entry =
|
|
platform_get_device_id(pdev);
|
|
struct mxs_dma_engine *mxs_dma;
|
|
struct resource *iores;
|
|
int ret, i;
|
|
|
|
mxs_dma = kzalloc(sizeof(*mxs_dma), GFP_KERNEL);
|
|
if (!mxs_dma)
|
|
return -ENOMEM;
|
|
|
|
mxs_dma->dev_id = id_entry->driver_data;
|
|
|
|
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!request_mem_region(iores->start, resource_size(iores),
|
|
pdev->name)) {
|
|
ret = -EBUSY;
|
|
goto err_request_region;
|
|
}
|
|
|
|
mxs_dma->base = ioremap(iores->start, resource_size(iores));
|
|
if (!mxs_dma->base) {
|
|
ret = -ENOMEM;
|
|
goto err_ioremap;
|
|
}
|
|
|
|
mxs_dma->clk = clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(mxs_dma->clk)) {
|
|
ret = PTR_ERR(mxs_dma->clk);
|
|
goto err_clk;
|
|
}
|
|
|
|
dma_cap_set(DMA_SLAVE, mxs_dma->dma_device.cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, mxs_dma->dma_device.cap_mask);
|
|
|
|
INIT_LIST_HEAD(&mxs_dma->dma_device.channels);
|
|
|
|
/* Initialize channel parameters */
|
|
for (i = 0; i < MXS_DMA_CHANNELS; i++) {
|
|
struct mxs_dma_chan *mxs_chan = &mxs_dma->mxs_chans[i];
|
|
|
|
mxs_chan->mxs_dma = mxs_dma;
|
|
mxs_chan->chan.device = &mxs_dma->dma_device;
|
|
dma_cookie_init(&mxs_chan->chan);
|
|
|
|
tasklet_init(&mxs_chan->tasklet, mxs_dma_tasklet,
|
|
(unsigned long) mxs_chan);
|
|
|
|
|
|
/* Add the channel to mxs_chan list */
|
|
list_add_tail(&mxs_chan->chan.device_node,
|
|
&mxs_dma->dma_device.channels);
|
|
}
|
|
|
|
ret = mxs_dma_init(mxs_dma);
|
|
if (ret)
|
|
goto err_init;
|
|
|
|
mxs_dma->dma_device.dev = &pdev->dev;
|
|
|
|
/* mxs_dma gets 65535 bytes maximum sg size */
|
|
mxs_dma->dma_device.dev->dma_parms = &mxs_dma->dma_parms;
|
|
dma_set_max_seg_size(mxs_dma->dma_device.dev, MAX_XFER_BYTES);
|
|
|
|
mxs_dma->dma_device.device_alloc_chan_resources = mxs_dma_alloc_chan_resources;
|
|
mxs_dma->dma_device.device_free_chan_resources = mxs_dma_free_chan_resources;
|
|
mxs_dma->dma_device.device_tx_status = mxs_dma_tx_status;
|
|
mxs_dma->dma_device.device_prep_slave_sg = mxs_dma_prep_slave_sg;
|
|
mxs_dma->dma_device.device_prep_dma_cyclic = mxs_dma_prep_dma_cyclic;
|
|
mxs_dma->dma_device.device_control = mxs_dma_control;
|
|
mxs_dma->dma_device.device_issue_pending = mxs_dma_issue_pending;
|
|
|
|
ret = dma_async_device_register(&mxs_dma->dma_device);
|
|
if (ret) {
|
|
dev_err(mxs_dma->dma_device.dev, "unable to register\n");
|
|
goto err_init;
|
|
}
|
|
|
|
dev_info(mxs_dma->dma_device.dev, "initialized\n");
|
|
|
|
return 0;
|
|
|
|
err_init:
|
|
clk_put(mxs_dma->clk);
|
|
err_clk:
|
|
iounmap(mxs_dma->base);
|
|
err_ioremap:
|
|
release_mem_region(iores->start, resource_size(iores));
|
|
err_request_region:
|
|
kfree(mxs_dma);
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_device_id mxs_dma_type[] = {
|
|
{
|
|
.name = "mxs-dma-apbh",
|
|
.driver_data = MXS_DMA_APBH,
|
|
}, {
|
|
.name = "mxs-dma-apbx",
|
|
.driver_data = MXS_DMA_APBX,
|
|
}, {
|
|
/* end of list */
|
|
}
|
|
};
|
|
|
|
static struct platform_driver mxs_dma_driver = {
|
|
.driver = {
|
|
.name = "mxs-dma",
|
|
},
|
|
.id_table = mxs_dma_type,
|
|
};
|
|
|
|
static int __init mxs_dma_module_init(void)
|
|
{
|
|
return platform_driver_probe(&mxs_dma_driver, mxs_dma_probe);
|
|
}
|
|
subsys_initcall(mxs_dma_module_init);
|