![Mark Brown](/assets/img/avatar_default.png)
NO_IRQ is only defined on some architectures - the general way to test for an invalid IRQ in the modern kernel is by comparing with zero. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Samuel Ortiz <sameo@openedhand.com>
1274 lines
38 KiB
C
1274 lines
38 KiB
C
/*
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* wm8350-core.c -- Device access for Wolfson WM8350
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*
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* Copyright 2007, 2008 Wolfson Microelectronics PLC.
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*
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* Author: Liam Girdwood, Mark Brown
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/bug.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/workqueue.h>
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#include <linux/mfd/wm8350/core.h>
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#include <linux/mfd/wm8350/audio.h>
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#include <linux/mfd/wm8350/comparator.h>
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#include <linux/mfd/wm8350/gpio.h>
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#include <linux/mfd/wm8350/pmic.h>
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#include <linux/mfd/wm8350/rtc.h>
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#include <linux/mfd/wm8350/supply.h>
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#include <linux/mfd/wm8350/wdt.h>
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#define WM8350_UNLOCK_KEY 0x0013
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#define WM8350_LOCK_KEY 0x0000
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#define WM8350_CLOCK_CONTROL_1 0x28
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#define WM8350_AIF_TEST 0x74
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/* debug */
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#define WM8350_BUS_DEBUG 0
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#if WM8350_BUS_DEBUG
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#define dump(regs, src) do { \
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int i_; \
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u16 *src_ = src; \
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printk(KERN_DEBUG); \
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for (i_ = 0; i_ < regs; i_++) \
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printk(" 0x%4.4x", *src_++); \
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printk("\n"); \
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} while (0);
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#else
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#define dump(bytes, src)
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#endif
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#define WM8350_LOCK_DEBUG 0
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#if WM8350_LOCK_DEBUG
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#define ldbg(format, arg...) printk(format, ## arg)
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#else
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#define ldbg(format, arg...)
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#endif
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/*
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* WM8350 Device IO
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*/
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static DEFINE_MUTEX(io_mutex);
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static DEFINE_MUTEX(reg_lock_mutex);
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static DEFINE_MUTEX(auxadc_mutex);
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/* Perform a physical read from the device.
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*/
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static int wm8350_phys_read(struct wm8350 *wm8350, u8 reg, int num_regs,
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u16 *dest)
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{
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int i, ret;
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int bytes = num_regs * 2;
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dev_dbg(wm8350->dev, "volatile read\n");
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ret = wm8350->read_dev(wm8350, reg, bytes, (char *)dest);
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for (i = reg; i < reg + num_regs; i++) {
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/* Cache is CPU endian */
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dest[i - reg] = be16_to_cpu(dest[i - reg]);
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/* Satisfy non-volatile bits from cache */
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dest[i - reg] &= wm8350_reg_io_map[i].vol;
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dest[i - reg] |= wm8350->reg_cache[i];
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/* Mask out non-readable bits */
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dest[i - reg] &= wm8350_reg_io_map[i].readable;
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}
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dump(num_regs, dest);
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return ret;
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}
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static int wm8350_read(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *dest)
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{
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int i;
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int end = reg + num_regs;
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int ret = 0;
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int bytes = num_regs * 2;
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if (wm8350->read_dev == NULL)
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return -ENODEV;
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if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
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dev_err(wm8350->dev, "invalid reg %x\n",
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reg + num_regs - 1);
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return -EINVAL;
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}
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dev_dbg(wm8350->dev,
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"%s R%d(0x%2.2x) %d regs\n", __func__, reg, reg, num_regs);
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#if WM8350_BUS_DEBUG
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/* we can _safely_ read any register, but warn if read not supported */
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for (i = reg; i < end; i++) {
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if (!wm8350_reg_io_map[i].readable)
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dev_warn(wm8350->dev,
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"reg R%d is not readable\n", i);
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}
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#endif
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/* if any volatile registers are required, then read back all */
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for (i = reg; i < end; i++)
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if (wm8350_reg_io_map[i].vol)
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return wm8350_phys_read(wm8350, reg, num_regs, dest);
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/* no volatiles, then cache is good */
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dev_dbg(wm8350->dev, "cache read\n");
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memcpy(dest, &wm8350->reg_cache[reg], bytes);
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dump(num_regs, dest);
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return ret;
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}
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static inline int is_reg_locked(struct wm8350 *wm8350, u8 reg)
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{
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if (reg == WM8350_SECURITY ||
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wm8350->reg_cache[WM8350_SECURITY] == WM8350_UNLOCK_KEY)
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return 0;
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if ((reg == WM8350_GPIO_CONFIGURATION_I_O) ||
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(reg >= WM8350_GPIO_FUNCTION_SELECT_1 &&
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reg <= WM8350_GPIO_FUNCTION_SELECT_4) ||
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(reg >= WM8350_BATTERY_CHARGER_CONTROL_1 &&
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reg <= WM8350_BATTERY_CHARGER_CONTROL_3))
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return 1;
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return 0;
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}
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static int wm8350_write(struct wm8350 *wm8350, u8 reg, int num_regs, u16 *src)
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{
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int i;
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int end = reg + num_regs;
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int bytes = num_regs * 2;
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if (wm8350->write_dev == NULL)
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return -ENODEV;
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if ((reg + num_regs - 1) > WM8350_MAX_REGISTER) {
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dev_err(wm8350->dev, "invalid reg %x\n",
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reg + num_regs - 1);
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return -EINVAL;
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}
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/* it's generally not a good idea to write to RO or locked registers */
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for (i = reg; i < end; i++) {
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if (!wm8350_reg_io_map[i].writable) {
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dev_err(wm8350->dev,
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"attempted write to read only reg R%d\n", i);
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return -EINVAL;
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}
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if (is_reg_locked(wm8350, i)) {
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dev_err(wm8350->dev,
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"attempted write to locked reg R%d\n", i);
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return -EINVAL;
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}
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src[i - reg] &= wm8350_reg_io_map[i].writable;
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wm8350->reg_cache[i] =
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(wm8350->reg_cache[i] & ~wm8350_reg_io_map[i].writable)
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| src[i - reg];
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src[i - reg] = cpu_to_be16(src[i - reg]);
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}
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/* Actually write it out */
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return wm8350->write_dev(wm8350, reg, bytes, (char *)src);
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}
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/*
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* Safe read, modify, write methods
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*/
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int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
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{
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u16 data;
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int err;
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mutex_lock(&io_mutex);
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err = wm8350_read(wm8350, reg, 1, &data);
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if (err) {
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dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
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goto out;
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}
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data &= ~mask;
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err = wm8350_write(wm8350, reg, 1, &data);
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if (err)
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dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
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out:
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mutex_unlock(&io_mutex);
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return err;
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}
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EXPORT_SYMBOL_GPL(wm8350_clear_bits);
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int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask)
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{
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u16 data;
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int err;
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mutex_lock(&io_mutex);
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err = wm8350_read(wm8350, reg, 1, &data);
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if (err) {
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dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
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goto out;
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}
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data |= mask;
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err = wm8350_write(wm8350, reg, 1, &data);
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if (err)
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dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
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out:
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mutex_unlock(&io_mutex);
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return err;
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}
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EXPORT_SYMBOL_GPL(wm8350_set_bits);
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u16 wm8350_reg_read(struct wm8350 *wm8350, int reg)
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{
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u16 data;
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int err;
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mutex_lock(&io_mutex);
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err = wm8350_read(wm8350, reg, 1, &data);
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if (err)
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dev_err(wm8350->dev, "read from reg R%d failed\n", reg);
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mutex_unlock(&io_mutex);
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return data;
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}
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EXPORT_SYMBOL_GPL(wm8350_reg_read);
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int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val)
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{
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int ret;
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u16 data = val;
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mutex_lock(&io_mutex);
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ret = wm8350_write(wm8350, reg, 1, &data);
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if (ret)
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dev_err(wm8350->dev, "write to reg R%d failed\n", reg);
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mutex_unlock(&io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(wm8350_reg_write);
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int wm8350_block_read(struct wm8350 *wm8350, int start_reg, int regs,
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u16 *dest)
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{
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int err = 0;
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mutex_lock(&io_mutex);
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err = wm8350_read(wm8350, start_reg, regs, dest);
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if (err)
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dev_err(wm8350->dev, "block read starting from R%d failed\n",
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start_reg);
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mutex_unlock(&io_mutex);
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return err;
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}
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EXPORT_SYMBOL_GPL(wm8350_block_read);
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int wm8350_block_write(struct wm8350 *wm8350, int start_reg, int regs,
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u16 *src)
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{
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int ret = 0;
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mutex_lock(&io_mutex);
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ret = wm8350_write(wm8350, start_reg, regs, src);
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if (ret)
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dev_err(wm8350->dev, "block write starting at R%d failed\n",
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start_reg);
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mutex_unlock(&io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(wm8350_block_write);
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int wm8350_reg_lock(struct wm8350 *wm8350)
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{
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u16 key = WM8350_LOCK_KEY;
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int ret;
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ldbg(__func__);
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mutex_lock(&io_mutex);
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ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
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if (ret)
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dev_err(wm8350->dev, "lock failed\n");
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mutex_unlock(&io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(wm8350_reg_lock);
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int wm8350_reg_unlock(struct wm8350 *wm8350)
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{
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u16 key = WM8350_UNLOCK_KEY;
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int ret;
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ldbg(__func__);
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mutex_lock(&io_mutex);
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ret = wm8350_write(wm8350, WM8350_SECURITY, 1, &key);
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if (ret)
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dev_err(wm8350->dev, "unlock failed\n");
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mutex_unlock(&io_mutex);
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return ret;
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}
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EXPORT_SYMBOL_GPL(wm8350_reg_unlock);
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static void wm8350_irq_call_handler(struct wm8350 *wm8350, int irq)
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{
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mutex_lock(&wm8350->irq_mutex);
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if (wm8350->irq[irq].handler)
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wm8350->irq[irq].handler(wm8350, irq, wm8350->irq[irq].data);
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else {
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dev_err(wm8350->dev, "irq %d nobody cared. now masked.\n",
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irq);
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wm8350_mask_irq(wm8350, irq);
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}
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mutex_unlock(&wm8350->irq_mutex);
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}
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/*
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* wm8350_irq_worker actually handles the interrupts. Since all
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* interrupts are clear on read the IRQ line will be reasserted and
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* the physical IRQ will be handled again if another interrupt is
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* asserted while we run - in the normal course of events this is a
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* rare occurrence so we save I2C/SPI reads.
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*/
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static void wm8350_irq_worker(struct work_struct *work)
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{
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struct wm8350 *wm8350 = container_of(work, struct wm8350, irq_work);
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u16 level_one, status1, status2, comp;
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/* TODO: Use block reads to improve performance? */
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level_one = wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS)
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& ~wm8350_reg_read(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK);
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status1 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_1)
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& ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_1_MASK);
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status2 = wm8350_reg_read(wm8350, WM8350_INT_STATUS_2)
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& ~wm8350_reg_read(wm8350, WM8350_INT_STATUS_2_MASK);
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comp = wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS)
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& ~wm8350_reg_read(wm8350, WM8350_COMPARATOR_INT_STATUS_MASK);
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/* over current */
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if (level_one & WM8350_OC_INT) {
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u16 oc;
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oc = wm8350_reg_read(wm8350, WM8350_OVER_CURRENT_INT_STATUS);
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oc &= ~wm8350_reg_read(wm8350,
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WM8350_OVER_CURRENT_INT_STATUS_MASK);
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if (oc & WM8350_OC_LS_EINT) /* limit switch */
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_OC_LS);
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}
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/* under voltage */
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if (level_one & WM8350_UV_INT) {
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u16 uv;
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uv = wm8350_reg_read(wm8350, WM8350_UNDER_VOLTAGE_INT_STATUS);
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uv &= ~wm8350_reg_read(wm8350,
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WM8350_UNDER_VOLTAGE_INT_STATUS_MASK);
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if (uv & WM8350_UV_DC1_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC1);
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if (uv & WM8350_UV_DC2_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC2);
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if (uv & WM8350_UV_DC3_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC3);
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if (uv & WM8350_UV_DC4_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC4);
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if (uv & WM8350_UV_DC5_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC5);
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if (uv & WM8350_UV_DC6_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_DC6);
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if (uv & WM8350_UV_LDO1_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO1);
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if (uv & WM8350_UV_LDO2_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO2);
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if (uv & WM8350_UV_LDO3_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO3);
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if (uv & WM8350_UV_LDO4_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_UV_LDO4);
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}
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/* charger, RTC */
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if (status1) {
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if (status1 & WM8350_CHG_BAT_HOT_EINT)
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wm8350_irq_call_handler(wm8350,
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WM8350_IRQ_CHG_BAT_HOT);
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if (status1 & WM8350_CHG_BAT_COLD_EINT)
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wm8350_irq_call_handler(wm8350,
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WM8350_IRQ_CHG_BAT_COLD);
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if (status1 & WM8350_CHG_BAT_FAIL_EINT)
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wm8350_irq_call_handler(wm8350,
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WM8350_IRQ_CHG_BAT_FAIL);
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if (status1 & WM8350_CHG_TO_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_TO);
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if (status1 & WM8350_CHG_END_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_END);
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if (status1 & WM8350_CHG_START_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_CHG_START);
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if (status1 & WM8350_CHG_FAST_RDY_EINT)
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wm8350_irq_call_handler(wm8350,
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WM8350_IRQ_CHG_FAST_RDY);
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if (status1 & WM8350_CHG_VBATT_LT_3P9_EINT)
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wm8350_irq_call_handler(wm8350,
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WM8350_IRQ_CHG_VBATT_LT_3P9);
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if (status1 & WM8350_CHG_VBATT_LT_3P1_EINT)
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wm8350_irq_call_handler(wm8350,
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WM8350_IRQ_CHG_VBATT_LT_3P1);
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if (status1 & WM8350_CHG_VBATT_LT_2P85_EINT)
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wm8350_irq_call_handler(wm8350,
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WM8350_IRQ_CHG_VBATT_LT_2P85);
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if (status1 & WM8350_RTC_ALM_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_ALM);
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if (status1 & WM8350_RTC_SEC_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_SEC);
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if (status1 & WM8350_RTC_PER_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_RTC_PER);
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}
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/* current sink, system, aux adc */
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if (status2) {
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if (status2 & WM8350_CS1_EINT)
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wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS1);
|
|
if (status2 & WM8350_CS2_EINT)
|
|
wm8350_irq_call_handler(wm8350, WM8350_IRQ_CS2);
|
|
|
|
if (status2 & WM8350_SYS_HYST_COMP_FAIL_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_SYS_HYST_COMP_FAIL);
|
|
if (status2 & WM8350_SYS_CHIP_GT115_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_SYS_CHIP_GT115);
|
|
if (status2 & WM8350_SYS_CHIP_GT140_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_SYS_CHIP_GT140);
|
|
if (status2 & WM8350_SYS_WDOG_TO_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_SYS_WDOG_TO);
|
|
|
|
if (status2 & WM8350_AUXADC_DATARDY_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_AUXADC_DATARDY);
|
|
if (status2 & WM8350_AUXADC_DCOMP4_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_AUXADC_DCOMP4);
|
|
if (status2 & WM8350_AUXADC_DCOMP3_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_AUXADC_DCOMP3);
|
|
if (status2 & WM8350_AUXADC_DCOMP2_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_AUXADC_DCOMP2);
|
|
if (status2 & WM8350_AUXADC_DCOMP1_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_AUXADC_DCOMP1);
|
|
|
|
if (status2 & WM8350_USB_LIMIT_EINT)
|
|
wm8350_irq_call_handler(wm8350, WM8350_IRQ_USB_LIMIT);
|
|
}
|
|
|
|
/* wake, codec, ext */
|
|
if (comp) {
|
|
if (comp & WM8350_WKUP_OFF_STATE_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_WKUP_OFF_STATE);
|
|
if (comp & WM8350_WKUP_HIB_STATE_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_WKUP_HIB_STATE);
|
|
if (comp & WM8350_WKUP_CONV_FAULT_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_WKUP_CONV_FAULT);
|
|
if (comp & WM8350_WKUP_WDOG_RST_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_WKUP_WDOG_RST);
|
|
if (comp & WM8350_WKUP_GP_PWR_ON_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_WKUP_GP_PWR_ON);
|
|
if (comp & WM8350_WKUP_ONKEY_EINT)
|
|
wm8350_irq_call_handler(wm8350, WM8350_IRQ_WKUP_ONKEY);
|
|
if (comp & WM8350_WKUP_GP_WAKEUP_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_WKUP_GP_WAKEUP);
|
|
|
|
if (comp & WM8350_CODEC_JCK_DET_L_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_CODEC_JCK_DET_L);
|
|
if (comp & WM8350_CODEC_JCK_DET_R_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_CODEC_JCK_DET_R);
|
|
if (comp & WM8350_CODEC_MICSCD_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_CODEC_MICSCD);
|
|
if (comp & WM8350_CODEC_MICD_EINT)
|
|
wm8350_irq_call_handler(wm8350, WM8350_IRQ_CODEC_MICD);
|
|
|
|
if (comp & WM8350_EXT_USB_FB_EINT)
|
|
wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_USB_FB);
|
|
if (comp & WM8350_EXT_WALL_FB_EINT)
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_EXT_WALL_FB);
|
|
if (comp & WM8350_EXT_BAT_FB_EINT)
|
|
wm8350_irq_call_handler(wm8350, WM8350_IRQ_EXT_BAT_FB);
|
|
}
|
|
|
|
if (level_one & WM8350_GP_INT) {
|
|
int i;
|
|
u16 gpio;
|
|
|
|
gpio = wm8350_reg_read(wm8350, WM8350_GPIO_INT_STATUS);
|
|
gpio &= ~wm8350_reg_read(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK);
|
|
|
|
for (i = 0; i < 12; i++) {
|
|
if (gpio & (1 << i))
|
|
wm8350_irq_call_handler(wm8350,
|
|
WM8350_IRQ_GPIO(i));
|
|
}
|
|
}
|
|
|
|
enable_irq(wm8350->chip_irq);
|
|
}
|
|
|
|
static irqreturn_t wm8350_irq(int irq, void *data)
|
|
{
|
|
struct wm8350 *wm8350 = data;
|
|
|
|
disable_irq_nosync(irq);
|
|
schedule_work(&wm8350->irq_work);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
int wm8350_register_irq(struct wm8350 *wm8350, int irq,
|
|
void (*handler) (struct wm8350 *, int, void *),
|
|
void *data)
|
|
{
|
|
if (irq < 0 || irq > WM8350_NUM_IRQ || !handler)
|
|
return -EINVAL;
|
|
|
|
if (wm8350->irq[irq].handler)
|
|
return -EBUSY;
|
|
|
|
mutex_lock(&wm8350->irq_mutex);
|
|
wm8350->irq[irq].handler = handler;
|
|
wm8350->irq[irq].data = data;
|
|
mutex_unlock(&wm8350->irq_mutex);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(wm8350_register_irq);
|
|
|
|
int wm8350_free_irq(struct wm8350 *wm8350, int irq)
|
|
{
|
|
if (irq < 0 || irq > WM8350_NUM_IRQ)
|
|
return -EINVAL;
|
|
|
|
mutex_lock(&wm8350->irq_mutex);
|
|
wm8350->irq[irq].handler = NULL;
|
|
mutex_unlock(&wm8350->irq_mutex);
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(wm8350_free_irq);
|
|
|
|
int wm8350_mask_irq(struct wm8350 *wm8350, int irq)
|
|
{
|
|
switch (irq) {
|
|
case WM8350_IRQ_CHG_BAT_HOT:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_BAT_HOT_EINT);
|
|
case WM8350_IRQ_CHG_BAT_COLD:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_BAT_COLD_EINT);
|
|
case WM8350_IRQ_CHG_BAT_FAIL:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_BAT_FAIL_EINT);
|
|
case WM8350_IRQ_CHG_TO:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_TO_EINT);
|
|
case WM8350_IRQ_CHG_END:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_END_EINT);
|
|
case WM8350_IRQ_CHG_START:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_START_EINT);
|
|
case WM8350_IRQ_CHG_FAST_RDY:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_FAST_RDY_EINT);
|
|
case WM8350_IRQ_RTC_PER:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_RTC_PER_EINT);
|
|
case WM8350_IRQ_RTC_SEC:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_RTC_SEC_EINT);
|
|
case WM8350_IRQ_RTC_ALM:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_RTC_ALM_EINT);
|
|
case WM8350_IRQ_CHG_VBATT_LT_3P9:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_VBATT_LT_3P9_EINT);
|
|
case WM8350_IRQ_CHG_VBATT_LT_3P1:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_VBATT_LT_3P1_EINT);
|
|
case WM8350_IRQ_CHG_VBATT_LT_2P85:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_VBATT_LT_2P85_EINT);
|
|
case WM8350_IRQ_CS1:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_CS1_EINT);
|
|
case WM8350_IRQ_CS2:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_CS2_EINT);
|
|
case WM8350_IRQ_USB_LIMIT:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_USB_LIMIT_EINT);
|
|
case WM8350_IRQ_AUXADC_DATARDY:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DATARDY_EINT);
|
|
case WM8350_IRQ_AUXADC_DCOMP4:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DCOMP4_EINT);
|
|
case WM8350_IRQ_AUXADC_DCOMP3:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DCOMP3_EINT);
|
|
case WM8350_IRQ_AUXADC_DCOMP2:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DCOMP2_EINT);
|
|
case WM8350_IRQ_AUXADC_DCOMP1:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DCOMP1_EINT);
|
|
case WM8350_IRQ_SYS_HYST_COMP_FAIL:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
|
|
case WM8350_IRQ_SYS_CHIP_GT115:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_SYS_CHIP_GT115_EINT);
|
|
case WM8350_IRQ_SYS_CHIP_GT140:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_SYS_CHIP_GT140_EINT);
|
|
case WM8350_IRQ_SYS_WDOG_TO:
|
|
return wm8350_set_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_SYS_WDOG_TO_EINT);
|
|
case WM8350_IRQ_UV_LDO4:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_LDO4_EINT);
|
|
case WM8350_IRQ_UV_LDO3:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_LDO3_EINT);
|
|
case WM8350_IRQ_UV_LDO2:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_LDO2_EINT);
|
|
case WM8350_IRQ_UV_LDO1:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_LDO1_EINT);
|
|
case WM8350_IRQ_UV_DC6:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC6_EINT);
|
|
case WM8350_IRQ_UV_DC5:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC5_EINT);
|
|
case WM8350_IRQ_UV_DC4:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC4_EINT);
|
|
case WM8350_IRQ_UV_DC3:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC3_EINT);
|
|
case WM8350_IRQ_UV_DC2:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC2_EINT);
|
|
case WM8350_IRQ_UV_DC1:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC1_EINT);
|
|
case WM8350_IRQ_OC_LS:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_OVER_CURRENT_INT_STATUS_MASK,
|
|
WM8350_IM_OC_LS_EINT);
|
|
case WM8350_IRQ_EXT_USB_FB:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_EXT_USB_FB_EINT);
|
|
case WM8350_IRQ_EXT_WALL_FB:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_EXT_WALL_FB_EINT);
|
|
case WM8350_IRQ_EXT_BAT_FB:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_EXT_BAT_FB_EINT);
|
|
case WM8350_IRQ_CODEC_JCK_DET_L:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_CODEC_JCK_DET_L_EINT);
|
|
case WM8350_IRQ_CODEC_JCK_DET_R:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_CODEC_JCK_DET_R_EINT);
|
|
case WM8350_IRQ_CODEC_MICSCD:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_CODEC_MICSCD_EINT);
|
|
case WM8350_IRQ_CODEC_MICD:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_CODEC_MICD_EINT);
|
|
case WM8350_IRQ_WKUP_OFF_STATE:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_OFF_STATE_EINT);
|
|
case WM8350_IRQ_WKUP_HIB_STATE:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_HIB_STATE_EINT);
|
|
case WM8350_IRQ_WKUP_CONV_FAULT:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_CONV_FAULT_EINT);
|
|
case WM8350_IRQ_WKUP_WDOG_RST:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_OFF_STATE_EINT);
|
|
case WM8350_IRQ_WKUP_GP_PWR_ON:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_GP_PWR_ON_EINT);
|
|
case WM8350_IRQ_WKUP_ONKEY:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_ONKEY_EINT);
|
|
case WM8350_IRQ_WKUP_GP_WAKEUP:
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_GP_WAKEUP_EINT);
|
|
case WM8350_IRQ_GPIO(0):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP0_EINT);
|
|
case WM8350_IRQ_GPIO(1):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP1_EINT);
|
|
case WM8350_IRQ_GPIO(2):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP2_EINT);
|
|
case WM8350_IRQ_GPIO(3):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP3_EINT);
|
|
case WM8350_IRQ_GPIO(4):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP4_EINT);
|
|
case WM8350_IRQ_GPIO(5):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP5_EINT);
|
|
case WM8350_IRQ_GPIO(6):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP6_EINT);
|
|
case WM8350_IRQ_GPIO(7):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP7_EINT);
|
|
case WM8350_IRQ_GPIO(8):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP8_EINT);
|
|
case WM8350_IRQ_GPIO(9):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP9_EINT);
|
|
case WM8350_IRQ_GPIO(10):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP10_EINT);
|
|
case WM8350_IRQ_GPIO(11):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP11_EINT);
|
|
case WM8350_IRQ_GPIO(12):
|
|
return wm8350_set_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP12_EINT);
|
|
default:
|
|
dev_warn(wm8350->dev, "Attempting to mask unknown IRQ %d\n",
|
|
irq);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(wm8350_mask_irq);
|
|
|
|
int wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
|
|
{
|
|
switch (irq) {
|
|
case WM8350_IRQ_CHG_BAT_HOT:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_BAT_HOT_EINT);
|
|
case WM8350_IRQ_CHG_BAT_COLD:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_BAT_COLD_EINT);
|
|
case WM8350_IRQ_CHG_BAT_FAIL:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_BAT_FAIL_EINT);
|
|
case WM8350_IRQ_CHG_TO:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_TO_EINT);
|
|
case WM8350_IRQ_CHG_END:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_END_EINT);
|
|
case WM8350_IRQ_CHG_START:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_START_EINT);
|
|
case WM8350_IRQ_CHG_FAST_RDY:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_FAST_RDY_EINT);
|
|
case WM8350_IRQ_RTC_PER:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_RTC_PER_EINT);
|
|
case WM8350_IRQ_RTC_SEC:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_RTC_SEC_EINT);
|
|
case WM8350_IRQ_RTC_ALM:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_RTC_ALM_EINT);
|
|
case WM8350_IRQ_CHG_VBATT_LT_3P9:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_VBATT_LT_3P9_EINT);
|
|
case WM8350_IRQ_CHG_VBATT_LT_3P1:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_VBATT_LT_3P1_EINT);
|
|
case WM8350_IRQ_CHG_VBATT_LT_2P85:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_1_MASK,
|
|
WM8350_IM_CHG_VBATT_LT_2P85_EINT);
|
|
case WM8350_IRQ_CS1:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_CS1_EINT);
|
|
case WM8350_IRQ_CS2:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_CS2_EINT);
|
|
case WM8350_IRQ_USB_LIMIT:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_USB_LIMIT_EINT);
|
|
case WM8350_IRQ_AUXADC_DATARDY:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DATARDY_EINT);
|
|
case WM8350_IRQ_AUXADC_DCOMP4:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DCOMP4_EINT);
|
|
case WM8350_IRQ_AUXADC_DCOMP3:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DCOMP3_EINT);
|
|
case WM8350_IRQ_AUXADC_DCOMP2:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DCOMP2_EINT);
|
|
case WM8350_IRQ_AUXADC_DCOMP1:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_AUXADC_DCOMP1_EINT);
|
|
case WM8350_IRQ_SYS_HYST_COMP_FAIL:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_SYS_HYST_COMP_FAIL_EINT);
|
|
case WM8350_IRQ_SYS_CHIP_GT115:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_SYS_CHIP_GT115_EINT);
|
|
case WM8350_IRQ_SYS_CHIP_GT140:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_SYS_CHIP_GT140_EINT);
|
|
case WM8350_IRQ_SYS_WDOG_TO:
|
|
return wm8350_clear_bits(wm8350, WM8350_INT_STATUS_2_MASK,
|
|
WM8350_IM_SYS_WDOG_TO_EINT);
|
|
case WM8350_IRQ_UV_LDO4:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_LDO4_EINT);
|
|
case WM8350_IRQ_UV_LDO3:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_LDO3_EINT);
|
|
case WM8350_IRQ_UV_LDO2:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_LDO2_EINT);
|
|
case WM8350_IRQ_UV_LDO1:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_LDO1_EINT);
|
|
case WM8350_IRQ_UV_DC6:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC6_EINT);
|
|
case WM8350_IRQ_UV_DC5:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC5_EINT);
|
|
case WM8350_IRQ_UV_DC4:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC4_EINT);
|
|
case WM8350_IRQ_UV_DC3:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC3_EINT);
|
|
case WM8350_IRQ_UV_DC2:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC2_EINT);
|
|
case WM8350_IRQ_UV_DC1:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_UNDER_VOLTAGE_INT_STATUS_MASK,
|
|
WM8350_IM_UV_DC1_EINT);
|
|
case WM8350_IRQ_OC_LS:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_OVER_CURRENT_INT_STATUS_MASK,
|
|
WM8350_IM_OC_LS_EINT);
|
|
case WM8350_IRQ_EXT_USB_FB:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_EXT_USB_FB_EINT);
|
|
case WM8350_IRQ_EXT_WALL_FB:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_EXT_WALL_FB_EINT);
|
|
case WM8350_IRQ_EXT_BAT_FB:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_EXT_BAT_FB_EINT);
|
|
case WM8350_IRQ_CODEC_JCK_DET_L:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_CODEC_JCK_DET_L_EINT);
|
|
case WM8350_IRQ_CODEC_JCK_DET_R:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_CODEC_JCK_DET_R_EINT);
|
|
case WM8350_IRQ_CODEC_MICSCD:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_CODEC_MICSCD_EINT);
|
|
case WM8350_IRQ_CODEC_MICD:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_CODEC_MICD_EINT);
|
|
case WM8350_IRQ_WKUP_OFF_STATE:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_OFF_STATE_EINT);
|
|
case WM8350_IRQ_WKUP_HIB_STATE:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_HIB_STATE_EINT);
|
|
case WM8350_IRQ_WKUP_CONV_FAULT:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_CONV_FAULT_EINT);
|
|
case WM8350_IRQ_WKUP_WDOG_RST:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_OFF_STATE_EINT);
|
|
case WM8350_IRQ_WKUP_GP_PWR_ON:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_GP_PWR_ON_EINT);
|
|
case WM8350_IRQ_WKUP_ONKEY:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_ONKEY_EINT);
|
|
case WM8350_IRQ_WKUP_GP_WAKEUP:
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_COMPARATOR_INT_STATUS_MASK,
|
|
WM8350_IM_WKUP_GP_WAKEUP_EINT);
|
|
case WM8350_IRQ_GPIO(0):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP0_EINT);
|
|
case WM8350_IRQ_GPIO(1):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP1_EINT);
|
|
case WM8350_IRQ_GPIO(2):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP2_EINT);
|
|
case WM8350_IRQ_GPIO(3):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP3_EINT);
|
|
case WM8350_IRQ_GPIO(4):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP4_EINT);
|
|
case WM8350_IRQ_GPIO(5):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP5_EINT);
|
|
case WM8350_IRQ_GPIO(6):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP6_EINT);
|
|
case WM8350_IRQ_GPIO(7):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP7_EINT);
|
|
case WM8350_IRQ_GPIO(8):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP8_EINT);
|
|
case WM8350_IRQ_GPIO(9):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP9_EINT);
|
|
case WM8350_IRQ_GPIO(10):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP10_EINT);
|
|
case WM8350_IRQ_GPIO(11):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP11_EINT);
|
|
case WM8350_IRQ_GPIO(12):
|
|
return wm8350_clear_bits(wm8350,
|
|
WM8350_GPIO_INT_STATUS_MASK,
|
|
WM8350_IM_GP12_EINT);
|
|
default:
|
|
dev_warn(wm8350->dev, "Attempting to unmask unknown IRQ %d\n",
|
|
irq);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(wm8350_unmask_irq);
|
|
|
|
/*
|
|
* Cache is always host endian.
|
|
*/
|
|
static int wm8350_create_cache(struct wm8350 *wm8350, int mode)
|
|
{
|
|
int i, ret = 0;
|
|
u16 value;
|
|
const u16 *reg_map;
|
|
|
|
switch (mode) {
|
|
#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_0
|
|
case 0:
|
|
reg_map = wm8350_mode0_defaults;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_1
|
|
case 1:
|
|
reg_map = wm8350_mode1_defaults;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_2
|
|
case 2:
|
|
reg_map = wm8350_mode2_defaults;
|
|
break;
|
|
#endif
|
|
#ifdef CONFIG_MFD_WM8350_CONFIG_MODE_3
|
|
case 3:
|
|
reg_map = wm8350_mode3_defaults;
|
|
break;
|
|
#endif
|
|
default:
|
|
dev_err(wm8350->dev, "Configuration mode %d not supported\n",
|
|
mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
wm8350->reg_cache =
|
|
kzalloc(sizeof(u16) * (WM8350_MAX_REGISTER + 1), GFP_KERNEL);
|
|
if (wm8350->reg_cache == NULL)
|
|
return -ENOMEM;
|
|
|
|
/* Read the initial cache state back from the device - this is
|
|
* a PMIC so the device many not be in a virgin state and we
|
|
* can't rely on the silicon values.
|
|
*/
|
|
for (i = 0; i < WM8350_MAX_REGISTER; i++) {
|
|
/* audio register range */
|
|
if (wm8350_reg_io_map[i].readable &&
|
|
(i < WM8350_CLOCK_CONTROL_1 || i > WM8350_AIF_TEST)) {
|
|
ret = wm8350->read_dev(wm8350, i, 2, (char *)&value);
|
|
if (ret < 0) {
|
|
dev_err(wm8350->dev,
|
|
"failed to read initial cache value\n");
|
|
goto out;
|
|
}
|
|
value = be16_to_cpu(value);
|
|
value &= wm8350_reg_io_map[i].readable;
|
|
wm8350->reg_cache[i] = value;
|
|
} else
|
|
wm8350->reg_cache[i] = reg_map[i];
|
|
}
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(wm8350_create_cache);
|
|
|
|
/*
|
|
* Register a client device. This is non-fatal since there is no need to
|
|
* fail the entire device init due to a single platform device failing.
|
|
*/
|
|
static void wm8350_client_dev_register(struct wm8350 *wm8350,
|
|
const char *name,
|
|
struct platform_device **pdev)
|
|
{
|
|
int ret;
|
|
|
|
*pdev = platform_device_alloc(name, -1);
|
|
if (pdev == NULL) {
|
|
dev_err(wm8350->dev, "Failed to allocate %s\n", name);
|
|
return;
|
|
}
|
|
|
|
(*pdev)->dev.parent = wm8350->dev;
|
|
platform_set_drvdata(*pdev, wm8350);
|
|
ret = platform_device_add(*pdev);
|
|
if (ret != 0) {
|
|
dev_err(wm8350->dev, "Failed to register %s: %d\n", name, ret);
|
|
platform_device_put(*pdev);
|
|
*pdev = NULL;
|
|
}
|
|
}
|
|
|
|
int wm8350_device_init(struct wm8350 *wm8350, int irq,
|
|
struct wm8350_platform_data *pdata)
|
|
{
|
|
int ret = -EINVAL;
|
|
u16 id1, id2, mask, mode;
|
|
|
|
/* get WM8350 revision and config mode */
|
|
wm8350->read_dev(wm8350, WM8350_RESET_ID, sizeof(id1), &id1);
|
|
wm8350->read_dev(wm8350, WM8350_ID, sizeof(id2), &id2);
|
|
|
|
id1 = be16_to_cpu(id1);
|
|
id2 = be16_to_cpu(id2);
|
|
|
|
if (id1 == 0x6143) {
|
|
switch ((id2 & WM8350_CHIP_REV_MASK) >> 12) {
|
|
case WM8350_REV_E:
|
|
dev_info(wm8350->dev, "Found Rev E device\n");
|
|
wm8350->rev = WM8350_REV_E;
|
|
break;
|
|
case WM8350_REV_F:
|
|
dev_info(wm8350->dev, "Found Rev F device\n");
|
|
wm8350->rev = WM8350_REV_F;
|
|
break;
|
|
case WM8350_REV_G:
|
|
dev_info(wm8350->dev, "Found Rev G device\n");
|
|
wm8350->rev = WM8350_REV_G;
|
|
break;
|
|
default:
|
|
/* For safety we refuse to run on unknown hardware */
|
|
dev_info(wm8350->dev, "Found unknown rev\n");
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
} else {
|
|
dev_info(wm8350->dev, "Device with ID %x is not a WM8350\n",
|
|
id1);
|
|
ret = -ENODEV;
|
|
goto err;
|
|
}
|
|
|
|
mode = id2 & WM8350_CONF_STS_MASK >> 10;
|
|
mask = id2 & WM8350_CUST_ID_MASK;
|
|
dev_info(wm8350->dev, "Config mode %d, ROM mask %d\n", mode, mask);
|
|
|
|
ret = wm8350_create_cache(wm8350, mode);
|
|
if (ret < 0) {
|
|
printk(KERN_ERR "wm8350: failed to create register cache\n");
|
|
return ret;
|
|
}
|
|
|
|
if (pdata->init) {
|
|
ret = pdata->init(wm8350);
|
|
if (ret != 0) {
|
|
dev_err(wm8350->dev, "Platform init() failed: %d\n",
|
|
ret);
|
|
goto err;
|
|
}
|
|
}
|
|
|
|
mutex_init(&wm8350->irq_mutex);
|
|
INIT_WORK(&wm8350->irq_work, wm8350_irq_worker);
|
|
if (irq) {
|
|
ret = request_irq(irq, wm8350_irq, 0,
|
|
"wm8350", wm8350);
|
|
if (ret != 0) {
|
|
dev_err(wm8350->dev, "Failed to request IRQ: %d\n",
|
|
ret);
|
|
goto err;
|
|
}
|
|
} else {
|
|
dev_err(wm8350->dev, "No IRQ configured\n");
|
|
goto err;
|
|
}
|
|
wm8350->chip_irq = irq;
|
|
|
|
wm8350_reg_write(wm8350, WM8350_SYSTEM_INTERRUPTS_MASK, 0x0);
|
|
|
|
wm8350_client_dev_register(wm8350, "wm8350-codec",
|
|
&(wm8350->codec.pdev));
|
|
wm8350_client_dev_register(wm8350, "wm8350-gpio",
|
|
&(wm8350->gpio.pdev));
|
|
wm8350_client_dev_register(wm8350, "wm8350-power",
|
|
&(wm8350->power.pdev));
|
|
wm8350_client_dev_register(wm8350, "wm8350-rtc", &(wm8350->rtc.pdev));
|
|
wm8350_client_dev_register(wm8350, "wm8350-wdt", &(wm8350->wdt.pdev));
|
|
|
|
return 0;
|
|
|
|
err:
|
|
kfree(wm8350->reg_cache);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(wm8350_device_init);
|
|
|
|
void wm8350_device_exit(struct wm8350 *wm8350)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(wm8350->pmic.pdev); i++)
|
|
platform_device_unregister(wm8350->pmic.pdev[i]);
|
|
|
|
platform_device_unregister(wm8350->wdt.pdev);
|
|
platform_device_unregister(wm8350->rtc.pdev);
|
|
platform_device_unregister(wm8350->power.pdev);
|
|
platform_device_unregister(wm8350->gpio.pdev);
|
|
platform_device_unregister(wm8350->codec.pdev);
|
|
|
|
free_irq(wm8350->chip_irq, wm8350);
|
|
flush_work(&wm8350->irq_work);
|
|
kfree(wm8350->reg_cache);
|
|
}
|
|
EXPORT_SYMBOL_GPL(wm8350_device_exit);
|
|
|
|
MODULE_DESCRIPTION("WM8350 AudioPlus PMIC core driver");
|
|
MODULE_LICENSE("GPL");
|