![Eli Cohen](/assets/img/avatar_default.png)
Add TSO support to the mlx4_ib driver. Signed-off-by: Eli Cohen <eli@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
843 lines
29 KiB
C
843 lines
29 KiB
C
/*
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* Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
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* Copyright (c) 2005 Mellanox Technologies. All rights reserved.
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* Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include <linux/mlx4/cmd.h>
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#include "fw.h"
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#include "icm.h"
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enum {
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MLX4_COMMAND_INTERFACE_MIN_REV = 2,
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MLX4_COMMAND_INTERFACE_MAX_REV = 3,
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MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
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};
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extern void __buggy_use_of_MLX4_GET(void);
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extern void __buggy_use_of_MLX4_PUT(void);
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#define MLX4_GET(dest, source, offset) \
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do { \
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void *__p = (char *) (source) + (offset); \
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switch (sizeof (dest)) { \
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case 1: (dest) = *(u8 *) __p; break; \
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case 2: (dest) = be16_to_cpup(__p); break; \
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case 4: (dest) = be32_to_cpup(__p); break; \
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case 8: (dest) = be64_to_cpup(__p); break; \
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default: __buggy_use_of_MLX4_GET(); \
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} \
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} while (0)
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#define MLX4_PUT(dest, source, offset) \
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do { \
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void *__d = ((char *) (dest) + (offset)); \
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switch (sizeof(source)) { \
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case 1: *(u8 *) __d = (source); break; \
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case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
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case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
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case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
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default: __buggy_use_of_MLX4_PUT(); \
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} \
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} while (0)
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static void dump_dev_cap_flags(struct mlx4_dev *dev, u32 flags)
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{
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static const char *fname[] = {
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[ 0] = "RC transport",
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[ 1] = "UC transport",
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[ 2] = "UD transport",
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[ 3] = "XRC transport",
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[ 4] = "reliable multicast",
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[ 5] = "FCoIB support",
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[ 6] = "SRQ support",
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[ 7] = "IPoIB checksum offload",
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[ 8] = "P_Key violation counter",
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[ 9] = "Q_Key violation counter",
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[10] = "VMM",
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[16] = "MW support",
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[17] = "APM support",
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[18] = "Atomic ops support",
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[19] = "Raw multicast support",
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[20] = "Address vector port checking support",
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[21] = "UD multicast support",
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[24] = "Demand paging support",
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[25] = "Router support"
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};
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int i;
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mlx4_dbg(dev, "DEV_CAP flags:\n");
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for (i = 0; i < ARRAY_SIZE(fname); ++i)
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if (fname[i] && (flags & (1 << i)))
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mlx4_dbg(dev, " %s\n", fname[i]);
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}
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int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
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{
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struct mlx4_cmd_mailbox *mailbox;
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u32 *outbox;
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u8 field;
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u16 size;
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u16 stat_rate;
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int err;
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int i;
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#define QUERY_DEV_CAP_OUT_SIZE 0x100
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#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
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#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
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#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
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#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
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#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
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#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
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#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
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#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
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#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
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#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
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#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
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#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
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#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
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#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
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#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
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#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
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#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
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#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
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#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
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#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
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#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
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#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
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#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
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#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
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#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
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#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
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#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
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#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
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#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
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#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
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#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
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#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
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#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
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#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
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#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
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#define QUERY_DEV_CAP_BF_OFFSET 0x4c
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#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
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#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
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#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
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#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
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#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
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#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
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#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
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#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
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#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
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#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
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#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
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#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
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#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
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#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
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#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
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#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
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#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
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#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
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#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
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#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
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#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
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#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
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#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x97
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#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
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#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
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mailbox = mlx4_alloc_cmd_mailbox(dev);
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if (IS_ERR(mailbox))
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return PTR_ERR(mailbox);
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outbox = mailbox->buf;
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err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
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MLX4_CMD_TIME_CLASS_A);
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if (err)
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goto out;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
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dev_cap->reserved_qps = 1 << (field & 0xf);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
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dev_cap->max_qps = 1 << (field & 0x1f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
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dev_cap->reserved_srqs = 1 << (field >> 4);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
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dev_cap->max_srqs = 1 << (field & 0x1f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
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dev_cap->max_cq_sz = 1 << field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
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dev_cap->reserved_cqs = 1 << (field & 0xf);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
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dev_cap->max_cqs = 1 << (field & 0x1f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
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dev_cap->max_mpts = 1 << (field & 0x3f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
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dev_cap->reserved_eqs = 1 << (field & 0xf);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
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dev_cap->max_eqs = 1 << (field & 0xf);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
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dev_cap->reserved_mtts = 1 << (field >> 4);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
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dev_cap->max_mrw_sz = 1 << field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
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dev_cap->reserved_mrws = 1 << (field & 0xf);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
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dev_cap->max_mtt_seg = 1 << (field & 0x3f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
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dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
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dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
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field &= 0x1f;
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if (!field)
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dev_cap->max_gso_sz = 0;
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else
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dev_cap->max_gso_sz = 1 << field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
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dev_cap->max_rdma_global = 1 << (field & 0x3f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
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dev_cap->local_ca_ack_delay = field & 0x1f;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
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dev_cap->num_ports = field & 0xf;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
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dev_cap->max_msg_sz = 1 << (field & 0x1f);
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MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
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dev_cap->stat_rate_support = stat_rate;
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MLX4_GET(dev_cap->flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
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dev_cap->reserved_uars = field >> 4;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
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dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
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dev_cap->min_page_sz = 1 << field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
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if (field & 0x80) {
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MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
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dev_cap->bf_reg_size = 1 << (field & 0x1f);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
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dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
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mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
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dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
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} else {
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dev_cap->bf_reg_size = 0;
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mlx4_dbg(dev, "BlueFlame not available\n");
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}
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
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dev_cap->max_sq_sg = field;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
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dev_cap->max_sq_desc_sz = size;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
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dev_cap->max_qp_per_mcg = 1 << field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
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dev_cap->reserved_mgms = field & 0xf;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
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dev_cap->max_mcgs = 1 << field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
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dev_cap->reserved_pds = field >> 4;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
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dev_cap->max_pds = 1 << (field & 0x3f);
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MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
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dev_cap->rdmarc_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
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dev_cap->qpc_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
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dev_cap->aux_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
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dev_cap->altc_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
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dev_cap->eqc_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
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dev_cap->cqc_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
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dev_cap->srq_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
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dev_cap->cmpt_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
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dev_cap->mtt_entry_sz = size;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
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dev_cap->dmpt_entry_sz = size;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
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dev_cap->max_srq_sz = 1 << field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
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dev_cap->max_qp_sz = 1 << field;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
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dev_cap->resize_srq = field & 1;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
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dev_cap->max_rq_sg = field;
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MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
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dev_cap->max_rq_desc_sz = size;
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MLX4_GET(dev_cap->bmme_flags, outbox,
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QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
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MLX4_GET(dev_cap->reserved_lkey, outbox,
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QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
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MLX4_GET(dev_cap->max_icm_sz, outbox,
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QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
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if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
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for (i = 1; i <= dev_cap->num_ports; ++i) {
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MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
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dev_cap->max_vl[i] = field >> 4;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
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dev_cap->max_mtu[i] = field >> 4;
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dev_cap->max_port_width[i] = field & 0xf;
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
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dev_cap->max_gids[i] = 1 << (field & 0xf);
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MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
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dev_cap->max_pkeys[i] = 1 << (field & 0xf);
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}
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} else {
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#define QUERY_PORT_MTU_OFFSET 0x01
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#define QUERY_PORT_WIDTH_OFFSET 0x06
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#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
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#define QUERY_PORT_MAX_VL_OFFSET 0x0b
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for (i = 1; i <= dev_cap->num_ports; ++i) {
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err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
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MLX4_CMD_TIME_CLASS_B);
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if (err)
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goto out;
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MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
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dev_cap->max_mtu[i] = field & 0xf;
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MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
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dev_cap->max_port_width[i] = field & 0xf;
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MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
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dev_cap->max_gids[i] = 1 << (field >> 4);
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dev_cap->max_pkeys[i] = 1 << (field & 0xf);
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MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
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dev_cap->max_vl[i] = field & 0xf;
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}
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}
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if (dev_cap->bmme_flags & 1)
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mlx4_dbg(dev, "Base MM extensions: yes "
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"(flags %d, rsvd L_Key %08x)\n",
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dev_cap->bmme_flags, dev_cap->reserved_lkey);
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|
else
|
|
mlx4_dbg(dev, "Base MM extensions: no\n");
|
|
|
|
/*
|
|
* Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
|
|
* we can't use any EQs whose doorbell falls on that page,
|
|
* even if the EQ itself isn't reserved.
|
|
*/
|
|
dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
|
|
dev_cap->reserved_eqs);
|
|
|
|
mlx4_dbg(dev, "Max ICM size %lld MB\n",
|
|
(unsigned long long) dev_cap->max_icm_sz >> 20);
|
|
mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
|
|
dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
|
|
mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
|
|
dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
|
|
mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
|
|
dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
|
|
mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
|
|
dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
|
|
mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
|
|
dev_cap->reserved_mrws, dev_cap->reserved_mtts);
|
|
mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
|
|
dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
|
|
mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
|
|
dev_cap->max_pds, dev_cap->reserved_mgms);
|
|
mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
|
|
dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
|
|
mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
|
|
dev_cap->local_ca_ack_delay, 128 << dev_cap->max_mtu[1],
|
|
dev_cap->max_port_width[1]);
|
|
mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
|
|
dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
|
|
mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
|
|
dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
|
|
mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
|
|
|
|
dump_dev_cap_flags(dev, dev_cap->flags);
|
|
|
|
out:
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
return err;
|
|
}
|
|
|
|
int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
|
|
{
|
|
struct mlx4_cmd_mailbox *mailbox;
|
|
struct mlx4_icm_iter iter;
|
|
__be64 *pages;
|
|
int lg;
|
|
int nent = 0;
|
|
int i;
|
|
int err = 0;
|
|
int ts = 0, tc = 0;
|
|
|
|
mailbox = mlx4_alloc_cmd_mailbox(dev);
|
|
if (IS_ERR(mailbox))
|
|
return PTR_ERR(mailbox);
|
|
memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
|
|
pages = mailbox->buf;
|
|
|
|
for (mlx4_icm_first(icm, &iter);
|
|
!mlx4_icm_last(&iter);
|
|
mlx4_icm_next(&iter)) {
|
|
/*
|
|
* We have to pass pages that are aligned to their
|
|
* size, so find the least significant 1 in the
|
|
* address or size and use that as our log2 size.
|
|
*/
|
|
lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
|
|
if (lg < MLX4_ICM_PAGE_SHIFT) {
|
|
mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
|
|
MLX4_ICM_PAGE_SIZE,
|
|
(unsigned long long) mlx4_icm_addr(&iter),
|
|
mlx4_icm_size(&iter));
|
|
err = -EINVAL;
|
|
goto out;
|
|
}
|
|
|
|
for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
|
|
if (virt != -1) {
|
|
pages[nent * 2] = cpu_to_be64(virt);
|
|
virt += 1 << lg;
|
|
}
|
|
|
|
pages[nent * 2 + 1] =
|
|
cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
|
|
(lg - MLX4_ICM_PAGE_SHIFT));
|
|
ts += 1 << (lg - 10);
|
|
++tc;
|
|
|
|
if (++nent == MLX4_MAILBOX_SIZE / 16) {
|
|
err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
|
|
MLX4_CMD_TIME_CLASS_B);
|
|
if (err)
|
|
goto out;
|
|
nent = 0;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (nent)
|
|
err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, MLX4_CMD_TIME_CLASS_B);
|
|
if (err)
|
|
goto out;
|
|
|
|
switch (op) {
|
|
case MLX4_CMD_MAP_FA:
|
|
mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
|
|
break;
|
|
case MLX4_CMD_MAP_ICM_AUX:
|
|
mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
|
|
break;
|
|
case MLX4_CMD_MAP_ICM:
|
|
mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
|
|
tc, ts, (unsigned long long) virt - (ts << 10));
|
|
break;
|
|
}
|
|
|
|
out:
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
return err;
|
|
}
|
|
|
|
int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
|
|
{
|
|
return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
|
|
}
|
|
|
|
int mlx4_UNMAP_FA(struct mlx4_dev *dev)
|
|
{
|
|
return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, MLX4_CMD_TIME_CLASS_B);
|
|
}
|
|
|
|
|
|
int mlx4_RUN_FW(struct mlx4_dev *dev)
|
|
{
|
|
return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, MLX4_CMD_TIME_CLASS_A);
|
|
}
|
|
|
|
int mlx4_QUERY_FW(struct mlx4_dev *dev)
|
|
{
|
|
struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
|
|
struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
|
|
struct mlx4_cmd_mailbox *mailbox;
|
|
u32 *outbox;
|
|
int err = 0;
|
|
u64 fw_ver;
|
|
u16 cmd_if_rev;
|
|
u8 lg;
|
|
|
|
#define QUERY_FW_OUT_SIZE 0x100
|
|
#define QUERY_FW_VER_OFFSET 0x00
|
|
#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
|
|
#define QUERY_FW_MAX_CMD_OFFSET 0x0f
|
|
#define QUERY_FW_ERR_START_OFFSET 0x30
|
|
#define QUERY_FW_ERR_SIZE_OFFSET 0x38
|
|
#define QUERY_FW_ERR_BAR_OFFSET 0x3c
|
|
|
|
#define QUERY_FW_SIZE_OFFSET 0x00
|
|
#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
|
|
#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
|
|
|
|
mailbox = mlx4_alloc_cmd_mailbox(dev);
|
|
if (IS_ERR(mailbox))
|
|
return PTR_ERR(mailbox);
|
|
outbox = mailbox->buf;
|
|
|
|
err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
|
|
MLX4_CMD_TIME_CLASS_A);
|
|
if (err)
|
|
goto out;
|
|
|
|
MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
|
|
/*
|
|
* FW subminor version is at more significant bits than minor
|
|
* version, so swap here.
|
|
*/
|
|
dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
|
|
((fw_ver & 0xffff0000ull) >> 16) |
|
|
((fw_ver & 0x0000ffffull) << 16);
|
|
|
|
MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
|
|
if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
|
|
cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
|
|
mlx4_err(dev, "Installed FW has unsupported "
|
|
"command interface revision %d.\n",
|
|
cmd_if_rev);
|
|
mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
|
|
(int) (dev->caps.fw_ver >> 32),
|
|
(int) (dev->caps.fw_ver >> 16) & 0xffff,
|
|
(int) dev->caps.fw_ver & 0xffff);
|
|
mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
|
|
MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
|
|
err = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
|
|
dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
|
|
|
|
MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
|
|
cmd->max_cmds = 1 << lg;
|
|
|
|
mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
|
|
(int) (dev->caps.fw_ver >> 32),
|
|
(int) (dev->caps.fw_ver >> 16) & 0xffff,
|
|
(int) dev->caps.fw_ver & 0xffff,
|
|
cmd_if_rev, cmd->max_cmds);
|
|
|
|
MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
|
|
MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
|
|
MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
|
|
fw->catas_bar = (fw->catas_bar >> 6) * 2;
|
|
|
|
mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
|
|
(unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
|
|
|
|
MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
|
|
MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
|
|
MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
|
|
fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
|
|
|
|
mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
|
|
|
|
/*
|
|
* Round up number of system pages needed in case
|
|
* MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
|
|
*/
|
|
fw->fw_pages =
|
|
ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
|
|
(PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
|
|
|
|
mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
|
|
(unsigned long long) fw->clr_int_base, fw->clr_int_bar);
|
|
|
|
out:
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
return err;
|
|
}
|
|
|
|
static void get_board_id(void *vsd, char *board_id)
|
|
{
|
|
int i;
|
|
|
|
#define VSD_OFFSET_SIG1 0x00
|
|
#define VSD_OFFSET_SIG2 0xde
|
|
#define VSD_OFFSET_MLX_BOARD_ID 0xd0
|
|
#define VSD_OFFSET_TS_BOARD_ID 0x20
|
|
|
|
#define VSD_SIGNATURE_TOPSPIN 0x5ad
|
|
|
|
memset(board_id, 0, MLX4_BOARD_ID_LEN);
|
|
|
|
if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
|
|
be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
|
|
strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
|
|
} else {
|
|
/*
|
|
* The board ID is a string but the firmware byte
|
|
* swaps each 4-byte word before passing it back to
|
|
* us. Therefore we need to swab it before printing.
|
|
*/
|
|
for (i = 0; i < 4; ++i)
|
|
((u32 *) board_id)[i] =
|
|
swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
|
|
}
|
|
}
|
|
|
|
int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
|
|
{
|
|
struct mlx4_cmd_mailbox *mailbox;
|
|
u32 *outbox;
|
|
int err;
|
|
|
|
#define QUERY_ADAPTER_OUT_SIZE 0x100
|
|
#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
|
|
#define QUERY_ADAPTER_VSD_OFFSET 0x20
|
|
|
|
mailbox = mlx4_alloc_cmd_mailbox(dev);
|
|
if (IS_ERR(mailbox))
|
|
return PTR_ERR(mailbox);
|
|
outbox = mailbox->buf;
|
|
|
|
err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
|
|
MLX4_CMD_TIME_CLASS_A);
|
|
if (err)
|
|
goto out;
|
|
|
|
MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
|
|
|
|
get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
|
|
adapter->board_id);
|
|
|
|
out:
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
return err;
|
|
}
|
|
|
|
int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
|
|
{
|
|
struct mlx4_cmd_mailbox *mailbox;
|
|
__be32 *inbox;
|
|
int err;
|
|
|
|
#define INIT_HCA_IN_SIZE 0x200
|
|
#define INIT_HCA_VERSION_OFFSET 0x000
|
|
#define INIT_HCA_VERSION 2
|
|
#define INIT_HCA_FLAGS_OFFSET 0x014
|
|
#define INIT_HCA_QPC_OFFSET 0x020
|
|
#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
|
|
#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
|
|
#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
|
|
#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
|
|
#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
|
|
#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
|
|
#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
|
|
#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
|
|
#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
|
|
#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
|
|
#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
|
|
#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
|
|
#define INIT_HCA_MCAST_OFFSET 0x0c0
|
|
#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
|
|
#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
|
|
#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
|
|
#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
|
|
#define INIT_HCA_TPT_OFFSET 0x0f0
|
|
#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
|
|
#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
|
|
#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
|
|
#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
|
|
#define INIT_HCA_UAR_OFFSET 0x120
|
|
#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
|
|
#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
|
|
|
|
mailbox = mlx4_alloc_cmd_mailbox(dev);
|
|
if (IS_ERR(mailbox))
|
|
return PTR_ERR(mailbox);
|
|
inbox = mailbox->buf;
|
|
|
|
memset(inbox, 0, INIT_HCA_IN_SIZE);
|
|
|
|
*((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
|
|
|
|
#if defined(__LITTLE_ENDIAN)
|
|
*(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
|
|
#elif defined(__BIG_ENDIAN)
|
|
*(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
|
|
#else
|
|
#error Host endianness not defined
|
|
#endif
|
|
/* Check port for UD address vector: */
|
|
*(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
|
|
|
|
/* Enable IPoIB checksumming if we can: */
|
|
if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
|
|
*(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
|
|
|
|
/* QPC/EEC/CQC/EQC/RDMARC attributes */
|
|
|
|
MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
|
|
MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
|
|
MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
|
|
MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
|
|
MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
|
|
|
|
/* multicast attributes */
|
|
|
|
MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
|
|
MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
|
|
MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
|
|
|
|
/* TPT attributes */
|
|
|
|
MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
|
|
MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
|
|
MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
|
|
|
|
/* UAR attributes */
|
|
|
|
MLX4_PUT(inbox, (u8) (PAGE_SHIFT - 12), INIT_HCA_UAR_PAGE_SZ_OFFSET);
|
|
MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
|
|
|
|
err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000);
|
|
|
|
if (err)
|
|
mlx4_err(dev, "INIT_HCA returns %d\n", err);
|
|
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
return err;
|
|
}
|
|
|
|
int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
|
|
{
|
|
struct mlx4_cmd_mailbox *mailbox;
|
|
u32 *inbox;
|
|
int err;
|
|
u32 flags;
|
|
u16 field;
|
|
|
|
if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
|
|
#define INIT_PORT_IN_SIZE 256
|
|
#define INIT_PORT_FLAGS_OFFSET 0x00
|
|
#define INIT_PORT_FLAG_SIG (1 << 18)
|
|
#define INIT_PORT_FLAG_NG (1 << 17)
|
|
#define INIT_PORT_FLAG_G0 (1 << 16)
|
|
#define INIT_PORT_VL_SHIFT 4
|
|
#define INIT_PORT_PORT_WIDTH_SHIFT 8
|
|
#define INIT_PORT_MTU_OFFSET 0x04
|
|
#define INIT_PORT_MAX_GID_OFFSET 0x06
|
|
#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
|
|
#define INIT_PORT_GUID0_OFFSET 0x10
|
|
#define INIT_PORT_NODE_GUID_OFFSET 0x18
|
|
#define INIT_PORT_SI_GUID_OFFSET 0x20
|
|
|
|
mailbox = mlx4_alloc_cmd_mailbox(dev);
|
|
if (IS_ERR(mailbox))
|
|
return PTR_ERR(mailbox);
|
|
inbox = mailbox->buf;
|
|
|
|
memset(inbox, 0, INIT_PORT_IN_SIZE);
|
|
|
|
flags = 0;
|
|
flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
|
|
flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
|
|
MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
|
|
|
|
field = 128 << dev->caps.mtu_cap[port];
|
|
MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
|
|
field = dev->caps.gid_table_len[port];
|
|
MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
|
|
field = dev->caps.pkey_table_len[port];
|
|
MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
|
|
|
|
err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
|
|
MLX4_CMD_TIME_CLASS_A);
|
|
|
|
mlx4_free_cmd_mailbox(dev, mailbox);
|
|
} else
|
|
err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
|
|
MLX4_CMD_TIME_CLASS_A);
|
|
|
|
return err;
|
|
}
|
|
EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
|
|
|
|
int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
|
|
{
|
|
return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000);
|
|
}
|
|
EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
|
|
|
|
int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
|
|
{
|
|
return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000);
|
|
}
|
|
|
|
int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
|
|
{
|
|
int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
|
|
MLX4_CMD_SET_ICM_SIZE,
|
|
MLX4_CMD_TIME_CLASS_A);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/*
|
|
* Round up number of system pages needed in case
|
|
* MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
|
|
*/
|
|
*aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
|
|
(PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int mlx4_NOP(struct mlx4_dev *dev)
|
|
{
|
|
/* Input modifier of 0x1f means "finish as soon as possible." */
|
|
return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100);
|
|
}
|