![Linus Torvalds](/assets/img/avatar_default.png)
Pull DMA-mapping fixes from Marek Szyprowski:
"Another set of fixes for ARM dma-mapping subsystem.
Commit e9da6e9905
replaced custom consistent buffer remapping code
with generic vmalloc areas. It however introduced some regressions
caused by limited support for allocations in atomic context. This
series contains fixes for those regressions.
For some subplatforms the default, pre-allocated pool for atomic
allocations turned out to be too small, so a function for setting its
size has been added.
Another set of patches adds support for atomic allocations to
IOMMU-aware DMA-mapping implementation.
The last part of this pull request contains two fixes for Contiguous
Memory Allocator, which relax too strict requirements."
* 'fixes-for-3.6' of git://git.linaro.org/people/mszyprowski/linux-dma-mapping:
ARM: dma-mapping: IOMMU allocates pages from atomic_pool with GFP_ATOMIC
ARM: dma-mapping: Introduce __atomic_get_pages() for __iommu_get_pages()
ARM: dma-mapping: Refactor out to introduce __in_atomic_pool
ARM: dma-mapping: atomic_pool with struct page **pages
ARM: Kirkwood: increase atomic coherent pool size
ARM: DMA-Mapping: print warning when atomic coherent allocation fails
ARM: DMA-Mapping: add function for setting coherent pool size from platform code
ARM: relax conditions required for enabling Contiguous Memory Allocator
mm: cma: fix alignment requirements for contiguous regions
706 lines
19 KiB
C
706 lines
19 KiB
C
/*
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* arch/arm/mach-kirkwood/common.c
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*
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* Core functions for Marvell Kirkwood SoCs
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/ata_platform.h>
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#include <linux/mtd/nand.h>
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#include <linux/dma-mapping.h>
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#include <linux/clk-provider.h>
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#include <linux/spinlock.h>
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#include <linux/mv643xx_i2c.h>
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#include <net/dsa.h>
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#include <asm/page.h>
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#include <asm/timex.h>
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#include <asm/kexec.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/kirkwood.h>
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#include <mach/bridge-regs.h>
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#include <plat/audio.h>
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#include <plat/cache-feroceon-l2.h>
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#include <plat/mvsdio.h>
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#include <plat/orion_nand.h>
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#include <plat/ehci-orion.h>
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#include <plat/common.h>
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#include <plat/time.h>
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#include <plat/addr-map.h>
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#include <plat/mv_xor.h>
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#include "common.h"
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/*****************************************************************************
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* I/O Address Mapping
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****************************************************************************/
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static struct map_desc kirkwood_io_desc[] __initdata = {
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{
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.virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
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.length = KIRKWOOD_PCIE_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
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.length = KIRKWOOD_PCIE1_IO_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = KIRKWOOD_REGS_VIRT_BASE,
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.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
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.length = KIRKWOOD_REGS_SIZE,
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.type = MT_DEVICE,
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},
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};
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void __init kirkwood_map_io(void)
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{
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iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
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}
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/*****************************************************************************
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* CLK tree
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****************************************************************************/
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static void enable_sata0(void)
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{
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/* Enable PLL and IVREF */
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writel(readl(SATA0_PHY_MODE_2) | 0xf, SATA0_PHY_MODE_2);
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/* Enable PHY */
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writel(readl(SATA0_IF_CTRL) & ~0x200, SATA0_IF_CTRL);
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}
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static void disable_sata0(void)
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{
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/* Disable PLL and IVREF */
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writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
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/* Disable PHY */
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writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
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}
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static void enable_sata1(void)
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{
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/* Enable PLL and IVREF */
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writel(readl(SATA1_PHY_MODE_2) | 0xf, SATA1_PHY_MODE_2);
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/* Enable PHY */
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writel(readl(SATA1_IF_CTRL) & ~0x200, SATA1_IF_CTRL);
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}
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static void disable_sata1(void)
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{
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/* Disable PLL and IVREF */
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writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
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/* Disable PHY */
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writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
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}
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static void disable_pcie0(void)
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{
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writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
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while (1)
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if (readl(PCIE_STATUS) & 0x1)
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break;
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writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
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}
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static void disable_pcie1(void)
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{
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u32 dev, rev;
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kirkwood_pcie_id(&dev, &rev);
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if (dev == MV88F6282_DEV_ID) {
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writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
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while (1)
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if (readl(PCIE1_STATUS) & 0x1)
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break;
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writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
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}
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}
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/* An extended version of the gated clk. This calls fn_en()/fn_dis
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* before enabling/disabling the clock. We use this to turn on/off
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* PHYs etc. */
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struct clk_gate_fn {
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struct clk_gate gate;
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void (*fn_en)(void);
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void (*fn_dis)(void);
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};
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#define to_clk_gate_fn(_gate) container_of(_gate, struct clk_gate_fn, gate)
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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static int clk_gate_fn_enable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
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int ret;
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ret = clk_gate_ops.enable(hw);
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if (!ret && gate_fn->fn_en)
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gate_fn->fn_en();
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return ret;
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}
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static void clk_gate_fn_disable(struct clk_hw *hw)
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{
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struct clk_gate *gate = to_clk_gate(hw);
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struct clk_gate_fn *gate_fn = to_clk_gate_fn(gate);
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if (gate_fn->fn_dis)
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gate_fn->fn_dis();
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clk_gate_ops.disable(hw);
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}
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static struct clk_ops clk_gate_fn_ops;
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static struct clk __init *clk_register_gate_fn(struct device *dev,
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const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 bit_idx,
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u8 clk_gate_flags, spinlock_t *lock,
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void (*fn_en)(void), void (*fn_dis)(void))
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{
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struct clk_gate_fn *gate_fn;
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struct clk *clk;
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struct clk_init_data init;
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gate_fn = kzalloc(sizeof(struct clk_gate_fn), GFP_KERNEL);
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if (!gate_fn) {
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pr_err("%s: could not allocate gated clk\n", __func__);
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return ERR_PTR(-ENOMEM);
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}
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init.name = name;
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init.ops = &clk_gate_fn_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_gate assignments */
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gate_fn->gate.reg = reg;
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gate_fn->gate.bit_idx = bit_idx;
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gate_fn->gate.flags = clk_gate_flags;
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gate_fn->gate.lock = lock;
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gate_fn->gate.hw.init = &init;
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gate_fn->fn_en = fn_en;
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gate_fn->fn_dis = fn_dis;
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/* ops is the gate ops, but with our enable/disable functions */
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if (clk_gate_fn_ops.enable != clk_gate_fn_enable ||
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clk_gate_fn_ops.disable != clk_gate_fn_disable) {
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clk_gate_fn_ops = clk_gate_ops;
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clk_gate_fn_ops.enable = clk_gate_fn_enable;
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clk_gate_fn_ops.disable = clk_gate_fn_disable;
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}
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clk = clk_register(dev, &gate_fn->gate.hw);
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if (IS_ERR(clk))
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kfree(gate_fn);
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return clk;
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}
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static DEFINE_SPINLOCK(gating_lock);
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static struct clk *tclk;
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static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
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{
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return clk_register_gate(NULL, name, "tclk", 0,
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(void __iomem *)CLOCK_GATING_CTRL,
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bit_idx, 0, &gating_lock);
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}
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static struct clk __init *kirkwood_register_gate_fn(const char *name,
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u8 bit_idx,
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void (*fn_en)(void),
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void (*fn_dis)(void))
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{
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return clk_register_gate_fn(NULL, name, "tclk", 0,
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(void __iomem *)CLOCK_GATING_CTRL,
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bit_idx, 0, &gating_lock, fn_en, fn_dis);
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}
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static struct clk *ge0, *ge1;
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void __init kirkwood_clk_init(void)
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{
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struct clk *runit, *sata0, *sata1, *usb0, *sdio;
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struct clk *crypto, *xor0, *xor1, *pex0, *pex1, *audio;
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tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
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CLK_IS_ROOT, kirkwood_tclk);
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runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT);
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ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
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ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
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sata0 = kirkwood_register_gate_fn("sata0", CGC_BIT_SATA0,
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enable_sata0, disable_sata0);
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sata1 = kirkwood_register_gate_fn("sata1", CGC_BIT_SATA1,
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enable_sata1, disable_sata1);
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usb0 = kirkwood_register_gate("usb0", CGC_BIT_USB0);
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sdio = kirkwood_register_gate("sdio", CGC_BIT_SDIO);
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crypto = kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
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xor0 = kirkwood_register_gate("xor0", CGC_BIT_XOR0);
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xor1 = kirkwood_register_gate("xor1", CGC_BIT_XOR1);
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pex0 = kirkwood_register_gate_fn("pex0", CGC_BIT_PEX0,
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NULL, disable_pcie0);
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pex1 = kirkwood_register_gate_fn("pex1", CGC_BIT_PEX1,
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NULL, disable_pcie1);
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audio = kirkwood_register_gate("audio", CGC_BIT_AUDIO);
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kirkwood_register_gate("tdm", CGC_BIT_TDM);
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kirkwood_register_gate("tsu", CGC_BIT_TSU);
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/* clkdev entries, mapping clks to devices */
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orion_clkdev_add(NULL, "orion_spi.0", runit);
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orion_clkdev_add(NULL, "orion_spi.1", runit);
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orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
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orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
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orion_clkdev_add(NULL, "orion_wdt", tclk);
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orion_clkdev_add("0", "sata_mv.0", sata0);
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orion_clkdev_add("1", "sata_mv.0", sata1);
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orion_clkdev_add(NULL, "orion-ehci.0", usb0);
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orion_clkdev_add(NULL, "orion_nand", runit);
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orion_clkdev_add(NULL, "mvsdio", sdio);
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orion_clkdev_add(NULL, "mv_crypto", crypto);
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orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".0", xor0);
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orion_clkdev_add(NULL, MV_XOR_SHARED_NAME ".1", xor1);
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orion_clkdev_add("0", "pcie", pex0);
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orion_clkdev_add("1", "pcie", pex1);
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orion_clkdev_add(NULL, "kirkwood-i2s", audio);
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orion_clkdev_add(NULL, MV64XXX_I2C_CTLR_NAME ".0", runit);
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/* Marvell says runit is used by SPI, UART, NAND, TWSI, ...,
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* so should never be gated.
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*/
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clk_prepare_enable(runit);
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}
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/*****************************************************************************
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* EHCI0
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****************************************************************************/
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void __init kirkwood_ehci_init(void)
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{
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orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
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}
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/*****************************************************************************
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* GE00
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****************************************************************************/
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void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
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{
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orion_ge00_init(eth_data,
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GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
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IRQ_KIRKWOOD_GE00_ERR, 1600);
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/* The interface forgets the MAC address assigned by u-boot if
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the clock is turned off, so claim the clk now. */
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clk_prepare_enable(ge0);
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}
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/*****************************************************************************
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* GE01
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****************************************************************************/
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void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
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{
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orion_ge01_init(eth_data,
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GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
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IRQ_KIRKWOOD_GE01_ERR, 1600);
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clk_prepare_enable(ge1);
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}
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/*****************************************************************************
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* Ethernet switch
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****************************************************************************/
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void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
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{
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orion_ge00_switch_init(d, irq);
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}
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/*****************************************************************************
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* NAND flash
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****************************************************************************/
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static struct resource kirkwood_nand_resource = {
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.flags = IORESOURCE_MEM,
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.start = KIRKWOOD_NAND_MEM_PHYS_BASE,
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.end = KIRKWOOD_NAND_MEM_PHYS_BASE +
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KIRKWOOD_NAND_MEM_SIZE - 1,
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};
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static struct orion_nand_data kirkwood_nand_data = {
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.cle = 0,
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.ale = 1,
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.width = 8,
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};
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static struct platform_device kirkwood_nand_flash = {
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.name = "orion_nand",
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.id = -1,
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.dev = {
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.platform_data = &kirkwood_nand_data,
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},
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.resource = &kirkwood_nand_resource,
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.num_resources = 1,
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};
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void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
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int chip_delay)
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{
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kirkwood_nand_data.parts = parts;
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kirkwood_nand_data.nr_parts = nr_parts;
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kirkwood_nand_data.chip_delay = chip_delay;
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platform_device_register(&kirkwood_nand_flash);
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}
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void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
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int (*dev_ready)(struct mtd_info *))
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{
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kirkwood_nand_data.parts = parts;
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kirkwood_nand_data.nr_parts = nr_parts;
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kirkwood_nand_data.dev_ready = dev_ready;
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platform_device_register(&kirkwood_nand_flash);
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}
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/*****************************************************************************
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* SoC RTC
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****************************************************************************/
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static void __init kirkwood_rtc_init(void)
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{
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orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
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}
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/*****************************************************************************
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* SATA
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****************************************************************************/
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void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
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{
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orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
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}
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/*****************************************************************************
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* SD/SDIO/MMC
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****************************************************************************/
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static struct resource mvsdio_resources[] = {
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[0] = {
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.start = SDIO_PHYS_BASE,
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.end = SDIO_PHYS_BASE + SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_KIRKWOOD_SDIO,
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.end = IRQ_KIRKWOOD_SDIO,
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.flags = IORESOURCE_IRQ,
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},
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};
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static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
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static struct platform_device kirkwood_sdio = {
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.name = "mvsdio",
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.id = -1,
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.dev = {
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.dma_mask = &mvsdio_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.num_resources = ARRAY_SIZE(mvsdio_resources),
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.resource = mvsdio_resources,
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};
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void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
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{
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u32 dev, rev;
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kirkwood_pcie_id(&dev, &rev);
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if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
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mvsdio_data->clock = 100000000;
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else
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mvsdio_data->clock = 200000000;
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kirkwood_sdio.dev.platform_data = mvsdio_data;
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platform_device_register(&kirkwood_sdio);
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}
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/*****************************************************************************
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* SPI
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****************************************************************************/
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void __init kirkwood_spi_init()
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{
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orion_spi_init(SPI_PHYS_BASE);
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}
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/*****************************************************************************
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* I2C
|
|
****************************************************************************/
|
|
void __init kirkwood_i2c_init(void)
|
|
{
|
|
orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* UART0
|
|
****************************************************************************/
|
|
|
|
void __init kirkwood_uart0_init(void)
|
|
{
|
|
orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
|
|
IRQ_KIRKWOOD_UART_0, tclk);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* UART1
|
|
****************************************************************************/
|
|
void __init kirkwood_uart1_init(void)
|
|
{
|
|
orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
|
|
IRQ_KIRKWOOD_UART_1, tclk);
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* Cryptographic Engines and Security Accelerator (CESA)
|
|
****************************************************************************/
|
|
void __init kirkwood_crypto_init(void)
|
|
{
|
|
orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
|
|
KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* XOR0
|
|
****************************************************************************/
|
|
void __init kirkwood_xor0_init(void)
|
|
{
|
|
orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
|
|
IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* XOR1
|
|
****************************************************************************/
|
|
void __init kirkwood_xor1_init(void)
|
|
{
|
|
orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
|
|
IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* Watchdog
|
|
****************************************************************************/
|
|
void __init kirkwood_wdt_init(void)
|
|
{
|
|
orion_wdt_init();
|
|
}
|
|
|
|
|
|
/*****************************************************************************
|
|
* Time handling
|
|
****************************************************************************/
|
|
void __init kirkwood_init_early(void)
|
|
{
|
|
orion_time_set_base(TIMER_VIRT_BASE);
|
|
|
|
/*
|
|
* Some Kirkwood devices allocate their coherent buffers from atomic
|
|
* context. Increase size of atomic coherent pool to make sure such
|
|
* the allocations won't fail.
|
|
*/
|
|
init_dma_coherent_pool_size(SZ_1M);
|
|
}
|
|
|
|
int kirkwood_tclk;
|
|
|
|
static int __init kirkwood_find_tclk(void)
|
|
{
|
|
u32 dev, rev;
|
|
|
|
kirkwood_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
|
|
if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
|
|
return 200000000;
|
|
|
|
return 166666667;
|
|
}
|
|
|
|
static void __init kirkwood_timer_init(void)
|
|
{
|
|
kirkwood_tclk = kirkwood_find_tclk();
|
|
|
|
orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
|
|
IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
|
|
}
|
|
|
|
struct sys_timer kirkwood_timer = {
|
|
.init = kirkwood_timer_init,
|
|
};
|
|
|
|
/*****************************************************************************
|
|
* Audio
|
|
****************************************************************************/
|
|
static struct resource kirkwood_i2s_resources[] = {
|
|
[0] = {
|
|
.start = AUDIO_PHYS_BASE,
|
|
.end = AUDIO_PHYS_BASE + SZ_16K - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = IRQ_KIRKWOOD_I2S,
|
|
.end = IRQ_KIRKWOOD_I2S,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
|
|
.burst = 128,
|
|
};
|
|
|
|
static struct platform_device kirkwood_i2s_device = {
|
|
.name = "kirkwood-i2s",
|
|
.id = -1,
|
|
.num_resources = ARRAY_SIZE(kirkwood_i2s_resources),
|
|
.resource = kirkwood_i2s_resources,
|
|
.dev = {
|
|
.platform_data = &kirkwood_i2s_data,
|
|
},
|
|
};
|
|
|
|
static struct platform_device kirkwood_pcm_device = {
|
|
.name = "kirkwood-pcm-audio",
|
|
.id = -1,
|
|
};
|
|
|
|
void __init kirkwood_audio_init(void)
|
|
{
|
|
platform_device_register(&kirkwood_i2s_device);
|
|
platform_device_register(&kirkwood_pcm_device);
|
|
}
|
|
|
|
/*****************************************************************************
|
|
* General
|
|
****************************************************************************/
|
|
/*
|
|
* Identify device ID and revision.
|
|
*/
|
|
char * __init kirkwood_id(void)
|
|
{
|
|
u32 dev, rev;
|
|
|
|
kirkwood_pcie_id(&dev, &rev);
|
|
|
|
if (dev == MV88F6281_DEV_ID) {
|
|
if (rev == MV88F6281_REV_Z0)
|
|
return "MV88F6281-Z0";
|
|
else if (rev == MV88F6281_REV_A0)
|
|
return "MV88F6281-A0";
|
|
else if (rev == MV88F6281_REV_A1)
|
|
return "MV88F6281-A1";
|
|
else
|
|
return "MV88F6281-Rev-Unsupported";
|
|
} else if (dev == MV88F6192_DEV_ID) {
|
|
if (rev == MV88F6192_REV_Z0)
|
|
return "MV88F6192-Z0";
|
|
else if (rev == MV88F6192_REV_A0)
|
|
return "MV88F6192-A0";
|
|
else if (rev == MV88F6192_REV_A1)
|
|
return "MV88F6192-A1";
|
|
else
|
|
return "MV88F6192-Rev-Unsupported";
|
|
} else if (dev == MV88F6180_DEV_ID) {
|
|
if (rev == MV88F6180_REV_A0)
|
|
return "MV88F6180-Rev-A0";
|
|
else if (rev == MV88F6180_REV_A1)
|
|
return "MV88F6180-Rev-A1";
|
|
else
|
|
return "MV88F6180-Rev-Unsupported";
|
|
} else if (dev == MV88F6282_DEV_ID) {
|
|
if (rev == MV88F6282_REV_A0)
|
|
return "MV88F6282-Rev-A0";
|
|
else if (rev == MV88F6282_REV_A1)
|
|
return "MV88F6282-Rev-A1";
|
|
else
|
|
return "MV88F6282-Rev-Unsupported";
|
|
} else {
|
|
return "Device-Unknown";
|
|
}
|
|
}
|
|
|
|
void __init kirkwood_l2_init(void)
|
|
{
|
|
#ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
|
|
writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
|
|
feroceon_l2_init(1);
|
|
#else
|
|
writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
|
|
feroceon_l2_init(0);
|
|
#endif
|
|
}
|
|
|
|
void __init kirkwood_init(void)
|
|
{
|
|
printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
|
|
kirkwood_id(), kirkwood_tclk);
|
|
|
|
/*
|
|
* Disable propagation of mbus errors to the CPU local bus,
|
|
* as this causes mbus errors (which can occur for example
|
|
* for PCI aborts) to throw CPU aborts, which we're not set
|
|
* up to deal with.
|
|
*/
|
|
writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
|
|
|
|
kirkwood_setup_cpu_mbus();
|
|
|
|
#ifdef CONFIG_CACHE_FEROCEON_L2
|
|
kirkwood_l2_init();
|
|
#endif
|
|
|
|
/* Setup root of clk tree */
|
|
kirkwood_clk_init();
|
|
|
|
/* internal devices that every board has */
|
|
kirkwood_rtc_init();
|
|
kirkwood_wdt_init();
|
|
kirkwood_xor0_init();
|
|
kirkwood_xor1_init();
|
|
kirkwood_crypto_init();
|
|
|
|
#ifdef CONFIG_KEXEC
|
|
kexec_reinit = kirkwood_enable_pcie;
|
|
#endif
|
|
}
|
|
|
|
void kirkwood_restart(char mode, const char *cmd)
|
|
{
|
|
/*
|
|
* Enable soft reset to assert RSTOUTn.
|
|
*/
|
|
writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
|
|
|
|
/*
|
|
* Assert soft reset.
|
|
*/
|
|
writel(SOFT_RESET, SYSTEM_SOFT_RESET);
|
|
|
|
while (1)
|
|
;
|
|
}
|