![Russell King](/assets/img/avatar_default.png)
Get rid of the unnecessary checks in dma_slave_config utilizing the DMA direction. This allows us to move the computation of cctl to the prepare function. Acked-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
481 lines
12 KiB
C
481 lines
12 KiB
C
/*
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* arch/arm/mach-spear3xx/spear320.c
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*
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* SPEAr320 machine source file
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*
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* Copyright (C) 2009-2012 ST Microelectronics
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* Viresh Kumar <viresh.linux@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#define pr_fmt(fmt) "SPEAr320: " fmt
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#include <linux/amba/pl022.h>
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#include <linux/amba/pl08x.h>
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#include <linux/amba/serial.h>
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#include <linux/of_platform.h>
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#include <asm/hardware/vic.h>
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#include <asm/mach/arch.h>
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#include <plat/shirq.h>
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#include <mach/generic.h>
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#include <mach/spear.h>
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#define SPEAR320_UART1_BASE UL(0xA3000000)
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#define SPEAR320_UART2_BASE UL(0xA4000000)
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#define SPEAR320_SSP0_BASE UL(0xA5000000)
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#define SPEAR320_SSP1_BASE UL(0xA6000000)
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/* Interrupt registers offsets and masks */
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#define SPEAR320_INT_STS_MASK_REG 0x04
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#define SPEAR320_INT_CLR_MASK_REG 0x04
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#define SPEAR320_INT_ENB_MASK_REG 0x08
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#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
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#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
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#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
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#define SPEAR320_EMI_IRQ_MASK (1 << 7)
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#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
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#define SPEAR320_SPP_IRQ_MASK (1 << 9)
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#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
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#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
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#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
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#define SPEAR320_UART1_IRQ_MASK (1 << 13)
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#define SPEAR320_UART2_IRQ_MASK (1 << 14)
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#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
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#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
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#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
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#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
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#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
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#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
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#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
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#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
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#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
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#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
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/* SPEAr320 Virtual irq definitions */
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/* IRQs sharing IRQ_GEN_RAS_1 */
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#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
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#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
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#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
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/* IRQs sharing IRQ_GEN_RAS_2 */
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#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
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/* IRQs sharing IRQ_GEN_RAS_3 */
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#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
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#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
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#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
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/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
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#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
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#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
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#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
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#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
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#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
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#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
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#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
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#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
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#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
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#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
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#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
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/* spear3xx shared irq */
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static struct shirq_dev_config shirq_ras1_config[] = {
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{
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.virq = SPEAR320_VIRQ_EMI,
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.status_mask = SPEAR320_EMI_IRQ_MASK,
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.clear_mask = SPEAR320_EMI_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_CLCD,
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.status_mask = SPEAR320_CLCD_IRQ_MASK,
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.clear_mask = SPEAR320_CLCD_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_SPP,
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.status_mask = SPEAR320_SPP_IRQ_MASK,
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.clear_mask = SPEAR320_SPP_IRQ_MASK,
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},
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};
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static struct spear_shirq shirq_ras1 = {
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.irq = SPEAR3XX_IRQ_GEN_RAS_1,
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.dev_config = shirq_ras1_config,
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.dev_count = ARRAY_SIZE(shirq_ras1_config),
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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static struct shirq_dev_config shirq_ras3_config[] = {
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{
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.virq = SPEAR320_VIRQ_PLGPIO,
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.enb_mask = SPEAR320_GPIO_IRQ_MASK,
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.status_mask = SPEAR320_GPIO_IRQ_MASK,
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.clear_mask = SPEAR320_GPIO_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_I2S_PLAY,
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.enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
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.status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
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.clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_I2S_REC,
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.enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
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.status_mask = SPEAR320_I2S_REC_IRQ_MASK,
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.clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
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},
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};
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static struct spear_shirq shirq_ras3 = {
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.irq = SPEAR3XX_IRQ_GEN_RAS_3,
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.dev_config = shirq_ras3_config,
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.dev_count = ARRAY_SIZE(shirq_ras3_config),
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.regs = {
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.enb_reg = SPEAR320_INT_ENB_MASK_REG,
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.reset_to_enb = 1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
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{
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.virq = SPEAR320_VIRQ_CANU,
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.status_mask = SPEAR320_CAN_U_IRQ_MASK,
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.clear_mask = SPEAR320_CAN_U_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_CANL,
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.status_mask = SPEAR320_CAN_L_IRQ_MASK,
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.clear_mask = SPEAR320_CAN_L_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_UART1,
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.status_mask = SPEAR320_UART1_IRQ_MASK,
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.clear_mask = SPEAR320_UART1_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_UART2,
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.status_mask = SPEAR320_UART2_IRQ_MASK,
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.clear_mask = SPEAR320_UART2_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_SSP1,
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.status_mask = SPEAR320_SSP1_IRQ_MASK,
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.clear_mask = SPEAR320_SSP1_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_SSP2,
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.status_mask = SPEAR320_SSP2_IRQ_MASK,
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.clear_mask = SPEAR320_SSP2_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_SMII0,
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.status_mask = SPEAR320_SMII0_IRQ_MASK,
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.clear_mask = SPEAR320_SMII0_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_MII1_SMII1,
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.status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
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.clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_WAKEUP_SMII0,
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.status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
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.clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
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.status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
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.clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
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}, {
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.virq = SPEAR320_VIRQ_I2C1,
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.status_mask = SPEAR320_I2C1_IRQ_MASK,
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.clear_mask = SPEAR320_I2C1_IRQ_MASK,
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},
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};
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static struct spear_shirq shirq_intrcomm_ras = {
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.irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
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.dev_config = shirq_intrcomm_ras_config,
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.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
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.regs = {
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.enb_reg = -1,
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.status_reg = SPEAR320_INT_STS_MASK_REG,
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.status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
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.clear_reg = SPEAR320_INT_CLR_MASK_REG,
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.reset_to_clear = 1,
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},
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};
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/* DMAC platform data's slave info */
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struct pl08x_channel_data spear320_dma_info[] = {
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{
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.bus_id = "uart0_rx",
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.min_signal = 2,
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.max_signal = 2,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "uart0_tx",
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.min_signal = 3,
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.max_signal = 3,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp0_rx",
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.min_signal = 8,
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.max_signal = 8,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp0_tx",
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.min_signal = 9,
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.max_signal = 9,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "i2c0_rx",
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.min_signal = 10,
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.max_signal = 10,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "i2c0_tx",
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.min_signal = 11,
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.max_signal = 11,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "irda",
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.min_signal = 12,
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.max_signal = 12,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "adc",
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.min_signal = 13,
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.max_signal = 13,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "to_jpeg",
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.min_signal = 14,
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.max_signal = 14,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "from_jpeg",
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.min_signal = 15,
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.max_signal = 15,
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.muxval = 0,
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.periph_buses = PL08X_AHB1,
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}, {
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.bus_id = "ssp1_rx",
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.min_signal = 0,
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.max_signal = 0,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ssp1_tx",
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.min_signal = 1,
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.max_signal = 1,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ssp2_rx",
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.min_signal = 2,
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.max_signal = 2,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "ssp2_tx",
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.min_signal = 3,
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.max_signal = 3,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart1_rx",
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.min_signal = 4,
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.max_signal = 4,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart1_tx",
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.min_signal = 5,
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.max_signal = 5,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart2_rx",
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.min_signal = 6,
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.max_signal = 6,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "uart2_tx",
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.min_signal = 7,
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.max_signal = 7,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2c1_rx",
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.min_signal = 8,
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.max_signal = 8,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2c1_tx",
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.min_signal = 9,
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.max_signal = 9,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2c2_rx",
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.min_signal = 10,
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.max_signal = 10,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2c2_tx",
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.min_signal = 11,
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.max_signal = 11,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2s_rx",
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.min_signal = 12,
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.max_signal = 12,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "i2s_tx",
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.min_signal = 13,
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.max_signal = 13,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "rs485_rx",
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.min_signal = 14,
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.max_signal = 14,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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}, {
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.bus_id = "rs485_tx",
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.min_signal = 15,
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.max_signal = 15,
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.muxval = 1,
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.periph_buses = PL08X_AHB2,
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},
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};
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static struct pl022_ssp_controller spear320_ssp_data[] = {
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{
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.bus_id = 1,
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.enable_dma = 1,
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "ssp1_tx",
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.dma_rx_param = "ssp1_rx",
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.num_chipselect = 2,
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}, {
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.bus_id = 2,
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.enable_dma = 1,
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "ssp2_tx",
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.dma_rx_param = "ssp2_rx",
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.num_chipselect = 2,
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}
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};
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static struct amba_pl011_data spear320_uart_data[] = {
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{
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "uart1_tx",
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.dma_rx_param = "uart1_rx",
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}, {
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.dma_filter = pl08x_filter_id,
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.dma_tx_param = "uart2_tx",
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.dma_rx_param = "uart2_rx",
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},
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};
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/* Add SPEAr310 auxdata to pass platform data */
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static struct of_dev_auxdata spear320_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL,
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&pl022_plat_data),
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OF_DEV_AUXDATA("arm,pl080", SPEAR3XX_ICM3_DMA_BASE, NULL,
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&pl080_plat_data),
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OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP0_BASE, NULL,
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&spear320_ssp_data[0]),
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OF_DEV_AUXDATA("arm,pl022", SPEAR320_SSP1_BASE, NULL,
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&spear320_ssp_data[1]),
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OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART1_BASE, NULL,
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&spear320_uart_data[0]),
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OF_DEV_AUXDATA("arm,pl011", SPEAR320_UART2_BASE, NULL,
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&spear320_uart_data[1]),
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{}
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};
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static void __init spear320_dt_init(void)
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{
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void __iomem *base;
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int ret;
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pl080_plat_data.slave_channels = spear320_dma_info;
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pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear320_dma_info);
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of_platform_populate(NULL, of_default_bus_match_table,
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spear320_auxdata_lookup, NULL);
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/* shared irq registration */
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base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
|
|
if (base) {
|
|
/* shirq 1 */
|
|
shirq_ras1.regs.base = base;
|
|
ret = spear_shirq_register(&shirq_ras1);
|
|
if (ret)
|
|
pr_err("Error registering Shared IRQ 1\n");
|
|
|
|
/* shirq 3 */
|
|
shirq_ras3.regs.base = base;
|
|
ret = spear_shirq_register(&shirq_ras3);
|
|
if (ret)
|
|
pr_err("Error registering Shared IRQ 3\n");
|
|
|
|
/* shirq 4 */
|
|
shirq_intrcomm_ras.regs.base = base;
|
|
ret = spear_shirq_register(&shirq_intrcomm_ras);
|
|
if (ret)
|
|
pr_err("Error registering Shared IRQ 4\n");
|
|
}
|
|
}
|
|
|
|
static const char * const spear320_dt_board_compat[] = {
|
|
"st,spear320",
|
|
"st,spear320-evb",
|
|
NULL,
|
|
};
|
|
|
|
struct map_desc spear320_io_desc[] __initdata = {
|
|
{
|
|
.virtual = VA_SPEAR320_SOC_CONFIG_BASE,
|
|
.pfn = __phys_to_pfn(SPEAR320_SOC_CONFIG_BASE),
|
|
.length = SZ_16M,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
static void __init spear320_map_io(void)
|
|
{
|
|
iotable_init(spear320_io_desc, ARRAY_SIZE(spear320_io_desc));
|
|
spear3xx_map_io();
|
|
}
|
|
|
|
DT_MACHINE_START(SPEAR320_DT, "ST SPEAr320 SoC with Flattened Device Tree")
|
|
.map_io = spear320_map_io,
|
|
.init_irq = spear3xx_dt_init_irq,
|
|
.handle_irq = vic_handle_irq,
|
|
.timer = &spear3xx_timer,
|
|
.init_machine = spear320_dt_init,
|
|
.restart = spear_restart,
|
|
.dt_compat = spear320_dt_board_compat,
|
|
MACHINE_END
|