![Stephen Warren](/assets/img/avatar_default.png)
Commit d91eeb0 "ARM: tegra: emc: device tree support" modified the EMC driver to create an EMC table from existing register settings when none was provided through platform data or device tree. This code wrote the wrong clock rate into the table; the actual rate in Hz, rather than the expected half-rate in KHz. This caused the BUG_ON in tegra2_emc_clk_round_rate() to fire, since that enormous rate could not be generated. Fixes: [ 2.425921] kernel BUG at arch/arm/mach-tegra/tegra2_clocks.c:1158! ... [ 2.618766] [<c001c0e8>] (tegra2_emc_clk_round_rate+0x58/0x70) from [<c00198b4>] (clk_round_rate+0x48/0x68) [ 2.628494] [<c00198b4>] (clk_round_rate+0x48/0x68) from [<c0019cc0>] (clk_set_rate_locked+0x40/0x68) [ 2.637707] [<c0019cc0>] (clk_set_rate_locked+0x40/0x68) from [<c0019d10>] (clk_set_rate+0x28/0x40) [ 2.646754] [<c0019d10>] (clk_set_rate+0x28/0x40) from [<c001ffc8>] (tegra_update_cpu_speed+0x54/0x144) [ 2.656144] [<c001ffc8>] (tegra_update_cpu_speed+0x54/0x144) from [<c002016c>] (tegra_target+0xb4/0xe0) [ 2.665538] [<c002016c>] (tegra_target+0xb4/0xe0) from [<c01a96c0>] (__cpufreq_driver_target+0x88/0xa4) [ 2.674931] [<c01a96c0>] (__cpufreq_driver_target+0x88/0xa4) from [<c01ac9d0>] (dbs_check_cpu+0x324/0x340) [ 2.684582] [<c01ac9d0>] (dbs_check_cpu+0x324/0x340) from [<c01aca40>] (do_dbs_timer+0x54/0xf4) [ 2.693277] [<c01aca40>] (do_dbs_timer+0x54/0xf4) from [<c00369a8>] (process_one_work+0x1d4/0x320) [ 2.702225] [<c00369a8>] (process_one_work+0x1d4/0x320) from [<c0036f34>] (worker_thread+0x134/0x230) [ 2.711437] [<c0036f34>] (worker_thread+0x134/0x230) from [<c003add0>] (kthread+0x80/0x8c) [ 2.719700] [<c003add0>] (kthread+0x80/0x8c) from [<c000ebf4>] (kernel_thread_exit+0x0/0x8) Reported-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Stephen Warren <swarren@nvidia.com> [olof: fixed calculation of printed values] Signed-off-by: Olof Johansson <olof@lixom.net>
357 lines
7.8 KiB
C
357 lines
7.8 KiB
C
/*
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* Copyright (C) 2011 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/tegra_emc.h>
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#include <mach/iomap.h>
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#include "tegra2_emc.h"
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#include "fuse.h"
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#ifdef CONFIG_TEGRA_EMC_SCALING_ENABLE
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static bool emc_enable = true;
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#else
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static bool emc_enable;
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#endif
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module_param(emc_enable, bool, 0644);
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static struct platform_device *emc_pdev;
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static void __iomem *emc_regbase;
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static inline void emc_writel(u32 val, unsigned long addr)
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{
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writel(val, emc_regbase + addr);
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}
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static inline u32 emc_readl(unsigned long addr)
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{
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return readl(emc_regbase + addr);
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}
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static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = {
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0x2c, /* RC */
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0x30, /* RFC */
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0x34, /* RAS */
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0x38, /* RP */
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0x3c, /* R2W */
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0x40, /* W2R */
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0x44, /* R2P */
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0x48, /* W2P */
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0x4c, /* RD_RCD */
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0x50, /* WR_RCD */
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0x54, /* RRD */
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0x58, /* REXT */
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0x5c, /* WDV */
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0x60, /* QUSE */
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0x64, /* QRST */
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0x68, /* QSAFE */
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0x6c, /* RDV */
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0x70, /* REFRESH */
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0x74, /* BURST_REFRESH_NUM */
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0x78, /* PDEX2WR */
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0x7c, /* PDEX2RD */
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0x80, /* PCHG2PDEN */
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0x84, /* ACT2PDEN */
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0x88, /* AR2PDEN */
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0x8c, /* RW2PDEN */
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0x90, /* TXSR */
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0x94, /* TCKE */
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0x98, /* TFAW */
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0x9c, /* TRPAB */
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0xa0, /* TCLKSTABLE */
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0xa4, /* TCLKSTOP */
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0xa8, /* TREFBW */
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0xac, /* QUSE_EXTRA */
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0x114, /* FBIO_CFG6 */
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0xb0, /* ODT_WRITE */
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0xb4, /* ODT_READ */
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0x104, /* FBIO_CFG5 */
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0x2bc, /* CFG_DIG_DLL */
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0x2c0, /* DLL_XFORM_DQS */
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0x2c4, /* DLL_XFORM_QUSE */
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0x2e0, /* ZCAL_REF_CNT */
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0x2e4, /* ZCAL_WAIT_CNT */
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0x2a8, /* AUTO_CAL_INTERVAL */
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0x2d0, /* CFG_CLKTRIM_0 */
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0x2d4, /* CFG_CLKTRIM_1 */
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0x2d8, /* CFG_CLKTRIM_2 */
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};
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/* Select the closest EMC rate that is higher than the requested rate */
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long tegra_emc_round_rate(unsigned long rate)
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{
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struct tegra_emc_pdata *pdata;
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int i;
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int best = -1;
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unsigned long distance = ULONG_MAX;
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if (!emc_pdev)
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return -EINVAL;
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pdata = emc_pdev->dev.platform_data;
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pr_debug("%s: %lu\n", __func__, rate);
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/*
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* The EMC clock rate is twice the bus rate, and the bus rate is
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* measured in kHz
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*/
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rate = rate / 2 / 1000;
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for (i = 0; i < pdata->num_tables; i++) {
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if (pdata->tables[i].rate >= rate &&
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(pdata->tables[i].rate - rate) < distance) {
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distance = pdata->tables[i].rate - rate;
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best = i;
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}
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}
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if (best < 0)
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return -EINVAL;
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pr_debug("%s: using %lu\n", __func__, pdata->tables[best].rate);
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return pdata->tables[best].rate * 2 * 1000;
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}
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/*
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* The EMC registers have shadow registers. When the EMC clock is updated
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* in the clock controller, the shadow registers are copied to the active
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* registers, allowing glitchless memory bus frequency changes.
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* This function updates the shadow registers for a new clock frequency,
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* and relies on the clock lock on the emc clock to avoid races between
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* multiple frequency changes
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*/
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int tegra_emc_set_rate(unsigned long rate)
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{
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struct tegra_emc_pdata *pdata;
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int i;
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int j;
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if (!emc_pdev)
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return -EINVAL;
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pdata = emc_pdev->dev.platform_data;
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/*
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* The EMC clock rate is twice the bus rate, and the bus rate is
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* measured in kHz
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*/
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rate = rate / 2 / 1000;
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for (i = 0; i < pdata->num_tables; i++)
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if (pdata->tables[i].rate == rate)
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break;
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if (i >= pdata->num_tables)
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return -EINVAL;
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pr_debug("%s: setting to %lu\n", __func__, rate);
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for (j = 0; j < TEGRA_EMC_NUM_REGS; j++)
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emc_writel(pdata->tables[i].regs[j], emc_reg_addr[j]);
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emc_readl(pdata->tables[i].regs[TEGRA_EMC_NUM_REGS - 1]);
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return 0;
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}
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#ifdef CONFIG_OF
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static struct device_node *tegra_emc_ramcode_devnode(struct device_node *np)
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{
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struct device_node *iter;
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u32 reg;
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for_each_child_of_node(np, iter) {
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if (of_property_read_u32(np, "nvidia,ram-code", ®))
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continue;
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if (reg == tegra_bct_strapping)
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return of_node_get(iter);
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}
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return NULL;
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}
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static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
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struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device_node *tnp, *iter;
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struct tegra_emc_pdata *pdata;
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int ret, i, num_tables;
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if (!np)
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return NULL;
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if (of_find_property(np, "nvidia,use-ram-code", NULL)) {
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tnp = tegra_emc_ramcode_devnode(np);
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if (!tnp)
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dev_warn(&pdev->dev,
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"can't find emc table for ram-code 0x%02x\n",
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tegra_bct_strapping);
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} else
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tnp = of_node_get(np);
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if (!tnp)
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return NULL;
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num_tables = 0;
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for_each_child_of_node(tnp, iter)
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if (of_device_is_compatible(iter, "nvidia,tegra20-emc-table"))
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num_tables++;
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if (!num_tables) {
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pdata = NULL;
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goto out;
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}
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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pdata->tables = devm_kzalloc(&pdev->dev,
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sizeof(*pdata->tables) * num_tables,
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GFP_KERNEL);
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i = 0;
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for_each_child_of_node(tnp, iter) {
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u32 prop;
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ret = of_property_read_u32(iter, "clock-frequency", &prop);
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if (ret) {
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dev_err(&pdev->dev, "no clock-frequency in %s\n",
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iter->full_name);
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continue;
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}
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pdata->tables[i].rate = prop;
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ret = of_property_read_u32_array(iter, "nvidia,emc-registers",
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pdata->tables[i].regs,
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TEGRA_EMC_NUM_REGS);
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if (ret) {
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dev_err(&pdev->dev,
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"malformed emc-registers property in %s\n",
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iter->full_name);
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continue;
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}
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i++;
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}
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pdata->num_tables = i;
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out:
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of_node_put(tnp);
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return pdata;
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}
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#else
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static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata(
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struct platform_device *pdev)
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{
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return NULL;
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}
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#endif
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static struct tegra_emc_pdata __devinit *tegra_emc_fill_pdata(struct platform_device *pdev)
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{
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struct clk *c = clk_get_sys(NULL, "emc");
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struct tegra_emc_pdata *pdata;
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unsigned long khz;
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int i;
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WARN_ON(pdev->dev.platform_data);
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BUG_ON(IS_ERR_OR_NULL(c));
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pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
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pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables),
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GFP_KERNEL);
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pdata->tables[0].rate = clk_get_rate(c) / 2 / 1000;
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for (i = 0; i < TEGRA_EMC_NUM_REGS; i++)
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pdata->tables[0].regs[i] = emc_readl(emc_reg_addr[i]);
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pdata->num_tables = 1;
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khz = pdata->tables[0].rate;
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dev_info(&pdev->dev, "no tables provided, using %ld kHz emc, "
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"%ld kHz mem\n", khz * 2, khz);
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return pdata;
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}
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static int __devinit tegra_emc_probe(struct platform_device *pdev)
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{
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struct tegra_emc_pdata *pdata;
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struct resource *res;
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if (!emc_enable) {
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dev_err(&pdev->dev, "disabled per module parameter\n");
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return -ENODEV;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "missing register base\n");
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return -ENOMEM;
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}
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emc_regbase = devm_request_and_ioremap(&pdev->dev, res);
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if (!emc_regbase) {
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dev_err(&pdev->dev, "failed to remap registers\n");
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return -ENOMEM;
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}
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pdata = pdev->dev.platform_data;
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if (!pdata)
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pdata = tegra_emc_dt_parse_pdata(pdev);
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if (!pdata)
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pdata = tegra_emc_fill_pdata(pdev);
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pdev->dev.platform_data = pdata;
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emc_pdev = pdev;
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return 0;
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}
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static struct of_device_id tegra_emc_of_match[] __devinitdata = {
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{ .compatible = "nvidia,tegra20-emc", },
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{ },
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};
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static struct platform_driver tegra_emc_driver = {
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.driver = {
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.name = "tegra-emc",
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.owner = THIS_MODULE,
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.of_match_table = tegra_emc_of_match,
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},
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.probe = tegra_emc_probe,
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};
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static int __init tegra_emc_init(void)
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{
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return platform_driver_register(&tegra_emc_driver);
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}
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device_initcall(tegra_emc_init);
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