![Sascha Hauer](/assets/img/avatar_default.png)
- Add necessary #ifdefs for CONFIG_COMMON_CLOCK - Add a global spinlock to protect the CCM registers Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
258 lines
6 KiB
C
258 lines
6 KiB
C
/*
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* Based on arch/arm/plat-omap/clock.c
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*
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* Copyright (C) 2004 - 2005 Nokia corporation
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* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
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* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
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* Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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/* #define DEBUG */
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/proc_fs.h>
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#include <linux/semaphore.h>
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#include <linux/string.h>
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#include <mach/clock.h>
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#include <mach/hardware.h>
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#ifndef CONFIG_COMMON_CLK
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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/*-------------------------------------------------------------------------
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* Standard clock functions defined in include/linux/clk.h
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*-------------------------------------------------------------------------*/
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static void __clk_disable(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return;
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WARN_ON(!clk->usecount);
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if (!(--clk->usecount)) {
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if (clk->disable)
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clk->disable(clk);
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__clk_disable(clk->parent);
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__clk_disable(clk->secondary);
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}
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}
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static int __clk_enable(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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if (clk->usecount++ == 0) {
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__clk_enable(clk->parent);
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__clk_enable(clk->secondary);
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if (clk->enable)
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clk->enable(clk);
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}
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return 0;
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}
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/* This function increments the reference count on the clock and enables the
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* clock if not already enabled. The parent clock tree is recursively enabled
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*/
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int clk_enable(struct clk *clk)
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{
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int ret = 0;
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if (clk == NULL || IS_ERR(clk))
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return -EINVAL;
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mutex_lock(&clocks_mutex);
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ret = __clk_enable(clk);
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mutex_unlock(&clocks_mutex);
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return ret;
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}
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EXPORT_SYMBOL(clk_enable);
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/* This function decrements the reference count on the clock and disables
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* the clock when reference count is 0. The parent clock tree is
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* recursively disabled
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*/
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void clk_disable(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return;
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mutex_lock(&clocks_mutex);
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__clk_disable(clk);
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mutex_unlock(&clocks_mutex);
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}
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EXPORT_SYMBOL(clk_disable);
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/* Retrieve the *current* clock rate. If the clock itself
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* does not provide a special calculation routine, ask
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* its parent and so on, until one is able to return
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* a valid clock rate
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*/
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (clk == NULL || IS_ERR(clk))
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return 0UL;
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if (clk->get_rate)
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return clk->get_rate(clk);
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return clk_get_rate(clk->parent);
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}
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EXPORT_SYMBOL(clk_get_rate);
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/* Round the requested clock rate to the nearest supported
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* rate that is less than or equal to the requested rate.
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* This is dependent on the clock's current parent.
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*/
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
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return 0;
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return clk->round_rate(clk, rate);
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}
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EXPORT_SYMBOL(clk_round_rate);
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/* Set the clock to the requested clock rate. The rate must
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* match a supported rate exactly based on what clk_round_rate returns
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*/
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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int ret = -EINVAL;
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if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
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return ret;
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mutex_lock(&clocks_mutex);
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ret = clk->set_rate(clk, rate);
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mutex_unlock(&clocks_mutex);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_rate);
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/* Set the clock's parent to another clock source */
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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int ret = -EINVAL;
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struct clk *old;
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if (clk == NULL || IS_ERR(clk) || parent == NULL ||
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IS_ERR(parent) || clk->set_parent == NULL)
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return ret;
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if (clk->usecount)
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clk_enable(parent);
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mutex_lock(&clocks_mutex);
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ret = clk->set_parent(clk, parent);
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if (ret == 0) {
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old = clk->parent;
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clk->parent = parent;
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} else {
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old = parent;
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}
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mutex_unlock(&clocks_mutex);
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if (clk->usecount)
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clk_disable(old);
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return ret;
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}
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EXPORT_SYMBOL(clk_set_parent);
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/* Retrieve the clock's parent clock source */
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struct clk *clk_get_parent(struct clk *clk)
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{
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struct clk *ret = NULL;
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if (clk == NULL || IS_ERR(clk))
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return ret;
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return clk->parent;
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}
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EXPORT_SYMBOL(clk_get_parent);
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#else
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/*
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* Lock to protect the clock module (ccm) registers. Used
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* on all i.MXs
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*/
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DEFINE_SPINLOCK(imx_ccm_lock);
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#endif /* CONFIG_COMMON_CLK */
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/*
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* Get the resulting clock rate from a PLL register value and the input
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* frequency. PLLs with this register layout can at least be found on
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* MX1, MX21, MX27 and MX31
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*
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* mfi + mfn / (mfd + 1)
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* f = 2 * f_ref * --------------------
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* pd + 1
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*/
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unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
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{
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long long ll;
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int mfn_abs;
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unsigned int mfi, mfn, mfd, pd;
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mfi = (reg_val >> 10) & 0xf;
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mfn = reg_val & 0x3ff;
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mfd = (reg_val >> 16) & 0x3ff;
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pd = (reg_val >> 26) & 0xf;
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mfi = mfi <= 5 ? 5 : mfi;
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mfn_abs = mfn;
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/* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
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* 2's complements number
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*/
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if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
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mfn_abs = 0x400 - mfn;
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freq *= 2;
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freq /= pd + 1;
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ll = (unsigned long long)freq * mfn_abs;
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do_div(ll, mfd + 1);
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if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
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ll = -ll;
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ll = (freq * mfi) + ll;
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return ll;
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}
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