![Ido Yariv](/assets/img/avatar_default.png)
Commit 7416401
("arm: davinci: Fix fallout from generic irq chip
conversion") introduced a bug, causing low level interrupt handlers to
get a bogus irq number as an argument. The gpio irq handler falsely
assumes that the handler data is the irq base number and that is no
longer true.
Set the irq handler data to be a pointer to the corresponding gpio
controller. The chained irq handler can then use it to extract both the
irq base number and the gpio registers structure.
Signed-off-by: Ido Yariv <ido@wizery.com>
CC: Thomas Gleixner <tglx@linutronix.de>
[nsekhar@ti.com: renamed "ctl" to "d", simplified indexing logic for chips and
took care of odd bank handling in irq handler]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
461 lines
12 KiB
C
461 lines
12 KiB
C
/*
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* TI DaVinci GPIO Support
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*
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* Copyright (c) 2006-2007 David Brownell
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* Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <mach/gpio.h>
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#include <asm/mach/irq.h>
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struct davinci_gpio_regs {
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u32 dir;
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u32 out_data;
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u32 set_data;
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u32 clr_data;
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u32 in_data;
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u32 set_rising;
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u32 clr_rising;
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u32 set_falling;
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u32 clr_falling;
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u32 intstat;
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};
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#define chip2controller(chip) \
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container_of(chip, struct davinci_gpio_controller, chip)
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static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)];
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static void __iomem *gpio_base;
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static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio)
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{
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void __iomem *ptr;
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if (gpio < 32 * 1)
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ptr = gpio_base + 0x10;
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else if (gpio < 32 * 2)
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ptr = gpio_base + 0x38;
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else if (gpio < 32 * 3)
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ptr = gpio_base + 0x60;
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else if (gpio < 32 * 4)
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ptr = gpio_base + 0x88;
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else if (gpio < 32 * 5)
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ptr = gpio_base + 0xb0;
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else
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ptr = NULL;
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return ptr;
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}
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static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
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{
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struct davinci_gpio_regs __iomem *g;
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g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
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return g;
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}
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static int __init davinci_gpio_irq_setup(void);
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/*--------------------------------------------------------------------------*/
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/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
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static inline int __davinci_direction(struct gpio_chip *chip,
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unsigned offset, bool out, int value)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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unsigned long flags;
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u32 temp;
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u32 mask = 1 << offset;
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spin_lock_irqsave(&d->lock, flags);
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temp = __raw_readl(&g->dir);
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if (out) {
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temp &= ~mask;
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__raw_writel(mask, value ? &g->set_data : &g->clr_data);
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} else {
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temp |= mask;
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}
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__raw_writel(temp, &g->dir);
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spin_unlock_irqrestore(&d->lock, flags);
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return 0;
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}
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static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
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{
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return __davinci_direction(chip, offset, false, 0);
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}
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static int
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davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
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{
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return __davinci_direction(chip, offset, true, value);
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}
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/*
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* Read the pin's value (works even if it's set up as output);
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* returns zero/nonzero.
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*
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* Note that changes are synched to the GPIO clock, so reading values back
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* right after you've set them may give old values.
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*/
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static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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return (1 << offset) & __raw_readl(&g->in_data);
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}
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/*
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* Assuming the pin is muxed as a gpio output, set its output value.
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*/
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static void
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davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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struct davinci_gpio_regs __iomem *g = d->regs;
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__raw_writel((1 << offset), value ? &g->set_data : &g->clr_data);
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}
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static int __init davinci_gpio_setup(void)
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{
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int i, base;
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unsigned ngpio;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct davinci_gpio_regs *regs;
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if (soc_info->gpio_type != GPIO_TYPE_DAVINCI)
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return 0;
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/*
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* The gpio banks conceptually expose a segmented bitmap,
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* and "ngpio" is one more than the largest zero-based
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* bit index that's valid.
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*/
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ngpio = soc_info->gpio_num;
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if (ngpio == 0) {
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pr_err("GPIO setup: how many GPIOs?\n");
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return -EINVAL;
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}
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if (WARN_ON(DAVINCI_N_GPIO < ngpio))
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ngpio = DAVINCI_N_GPIO;
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gpio_base = ioremap(soc_info->gpio_base, SZ_4K);
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if (WARN_ON(!gpio_base))
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return -ENOMEM;
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for (i = 0, base = 0; base < ngpio; i++, base += 32) {
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chips[i].chip.label = "DaVinci";
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chips[i].chip.direction_input = davinci_direction_in;
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chips[i].chip.get = davinci_gpio_get;
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chips[i].chip.direction_output = davinci_direction_out;
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chips[i].chip.set = davinci_gpio_set;
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chips[i].chip.base = base;
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chips[i].chip.ngpio = ngpio - base;
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if (chips[i].chip.ngpio > 32)
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chips[i].chip.ngpio = 32;
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spin_lock_init(&chips[i].lock);
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regs = gpio2regs(base);
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chips[i].regs = regs;
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chips[i].set_data = ®s->set_data;
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chips[i].clr_data = ®s->clr_data;
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chips[i].in_data = ®s->in_data;
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gpiochip_add(&chips[i].chip);
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}
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soc_info->gpio_ctlrs = chips;
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soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32);
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davinci_gpio_irq_setup();
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return 0;
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}
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pure_initcall(davinci_gpio_setup);
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/*--------------------------------------------------------------------------*/
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/*
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* We expect irqs will normally be set up as input pins, but they can also be
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* used as output pins ... which is convenient for testing.
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*
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* NOTE: The first few GPIOs also have direct INTC hookups in addition
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* to their GPIOBNK0 irq, with a bit less overhead.
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*
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* All those INTC hookups (direct, plus several IRQ banks) can also
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* serve as EDMA event triggers.
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*/
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static void gpio_irq_disable(struct irq_data *d)
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{
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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__raw_writel(mask, &g->clr_falling);
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__raw_writel(mask, &g->clr_rising);
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}
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static void gpio_irq_enable(struct irq_data *d)
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{
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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unsigned status = irqd_get_trigger_type(d);
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status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
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if (!status)
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status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
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if (status & IRQ_TYPE_EDGE_FALLING)
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__raw_writel(mask, &g->set_falling);
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if (status & IRQ_TYPE_EDGE_RISING)
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__raw_writel(mask, &g->set_rising);
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}
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static int gpio_irq_type(struct irq_data *d, unsigned trigger)
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{
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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return 0;
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}
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static struct irq_chip gpio_irqchip = {
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.name = "GPIO",
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.irq_enable = gpio_irq_enable,
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.irq_disable = gpio_irq_disable,
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.irq_set_type = gpio_irq_type,
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.flags = IRQCHIP_SET_TYPE_MASKED,
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};
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static void
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gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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{
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struct davinci_gpio_regs __iomem *g;
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u32 mask = 0xffff;
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struct davinci_gpio_controller *d;
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d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc);
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g = (struct davinci_gpio_regs __iomem *)d->regs;
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/* we only care about one bank */
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if (irq & 1)
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mask <<= 16;
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/* temporarily mask (level sensitive) parent IRQ */
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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while (1) {
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u32 status;
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int n;
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int res;
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/* ack any irqs */
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status = __raw_readl(&g->intstat) & mask;
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if (!status)
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break;
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__raw_writel(status, &g->intstat);
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/* now demux them to the right lowlevel handler */
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n = d->irq_base;
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if (irq & 1) {
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n += 16;
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status >>= 16;
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}
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while (status) {
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res = ffs(status);
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n += res;
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generic_handle_irq(n - 1);
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status >>= res;
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}
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}
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desc->irq_data.chip->irq_unmask(&desc->irq_data);
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/* now it may re-trigger */
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}
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static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_gpio_controller *d = chip2controller(chip);
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if (d->irq_base >= 0)
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return d->irq_base + offset;
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else
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return -ENODEV;
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}
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static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
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{
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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/* NOTE: we assume for now that only irqs in the first gpio_chip
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* can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
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*/
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if (offset < soc_info->gpio_unbanked)
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return soc_info->gpio_irq + offset;
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else
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return -ENODEV;
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}
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static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
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{
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struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
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u32 mask = (u32) irq_data_get_irq_handler_data(d);
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if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
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return -EINVAL;
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
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? &g->set_falling : &g->clr_falling);
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__raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
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? &g->set_rising : &g->clr_rising);
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return 0;
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}
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/*
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* NOTE: for suspend/resume, probably best to make a platform_device with
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* suspend_late/resume_resume calls hooking into results of the set_wake()
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* calls ... so if no gpios are wakeup events the clock can be disabled,
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* with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
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* (dm6446) can be set appropriately for GPIOV33 pins.
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*/
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static int __init davinci_gpio_irq_setup(void)
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{
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unsigned gpio, irq, bank;
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struct clk *clk;
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u32 binten = 0;
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unsigned ngpio, bank_irq;
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struct davinci_soc_info *soc_info = &davinci_soc_info;
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struct davinci_gpio_regs __iomem *g;
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ngpio = soc_info->gpio_num;
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bank_irq = soc_info->gpio_irq;
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if (bank_irq == 0) {
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printk(KERN_ERR "Don't know first GPIO bank IRQ.\n");
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return -EINVAL;
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}
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clk = clk_get(NULL, "gpio");
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if (IS_ERR(clk)) {
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printk(KERN_ERR "Error %ld getting gpio clock?\n",
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PTR_ERR(clk));
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return PTR_ERR(clk);
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}
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clk_enable(clk);
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/* Arrange gpio_to_irq() support, handling either direct IRQs or
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* banked IRQs. Having GPIOs in the first GPIO bank use direct
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* IRQs, while the others use banked IRQs, would need some setup
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* tweaks to recognize hardware which can do that.
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*/
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for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) {
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chips[bank].chip.to_irq = gpio_to_irq_banked;
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chips[bank].irq_base = soc_info->gpio_unbanked
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? -EINVAL
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: (soc_info->intc_irq_num + gpio);
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}
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/*
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* AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
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* controller only handling trigger modes. We currently assume no
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* IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
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*/
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if (soc_info->gpio_unbanked) {
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static struct irq_chip gpio_irqchip_unbanked;
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/* pass "bank 0" GPIO IRQs to AINTC */
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chips[0].chip.to_irq = gpio_to_irq_unbanked;
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binten = BIT(0);
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/* AINTC handles mask/unmask; GPIO handles triggering */
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irq = bank_irq;
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gpio_irqchip_unbanked = *irq_get_chip(irq);
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gpio_irqchip_unbanked.name = "GPIO-AINTC";
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gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
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/* default trigger: both edges */
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g = gpio2regs(0);
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__raw_writel(~0, &g->set_falling);
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__raw_writel(~0, &g->set_rising);
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/* set the direct IRQs up to use that irqchip */
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for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
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irq_set_chip(irq, &gpio_irqchip_unbanked);
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irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
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irq_set_chip_data(irq, (__force void *)g);
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irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
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}
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goto done;
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}
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/*
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* Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
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* then chain through our own handler.
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*/
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for (gpio = 0, irq = gpio_to_irq(0), bank = 0;
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gpio < ngpio;
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bank++, bank_irq++) {
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unsigned i;
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/* disabled by default, enabled only as needed */
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g = gpio2regs(gpio);
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__raw_writel(~0, &g->clr_falling);
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__raw_writel(~0, &g->clr_rising);
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/* set up all irqs in this bank */
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irq_set_chained_handler(bank_irq, gpio_irq_handler);
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/*
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* Each chip handles 32 gpios, and each irq bank consists of 16
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* gpio irqs. Pass the irq bank's corresponding controller to
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* the chained irq handler.
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*/
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irq_set_handler_data(bank_irq, &chips[gpio / 32]);
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for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
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irq_set_chip(irq, &gpio_irqchip);
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irq_set_chip_data(irq, (__force void *)g);
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irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
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irq_set_handler(irq, handle_simple_irq);
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set_irq_flags(irq, IRQF_VALID);
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}
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binten |= BIT(bank);
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}
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done:
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/* BINTEN -- per-bank interrupt enable. genirq would also let these
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* bits be set/cleared dynamically.
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*/
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__raw_writel(binten, gpio_base + 0x08);
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printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0));
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return 0;
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}
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