306e5e50a3
Simple enough to be compatible with simulation environments, such as verilated systems, QEMU and other targets supporting OpenRISC SMP. This also supports our base FPGA SoC's if the cpu frequency is upped to 50Mhz. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne@gmail.com: Added defconfig] Signed-off-by: Stafford Horne <shorne@gmail.com>
64 lines
1.1 KiB
Plaintext
64 lines
1.1 KiB
Plaintext
/dts-v1/;
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/ {
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compatible = "opencores,or1ksim";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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aliases {
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uart0 = &serial0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "uart0:115200";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x02000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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clock-frequency = <20000000>;
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};
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cpu@1 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <1>;
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clock-frequency = <20000000>;
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};
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};
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ompic: ompic@98000000 {
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compatible = "openrisc,ompic";
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reg = <0x98000000 16>;
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interrupt-controller;
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#interrupt-cells = <0>;
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interrupts = <1>;
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};
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/*
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* OR1K PIC is built into CPU and accessed via special purpose
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* registers. It is not addressable and, hence, has no 'reg'
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* property.
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*/
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pic: pic {
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compatible = "opencores,or1k-pic-level";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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serial0: serial@90000000 {
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compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
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reg = <0x90000000 0x100>;
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interrupts = <2>;
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clock-frequency = <20000000>;
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};
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};
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