71e8831f64
Dynamic Memory Manager (DMM) is a hardware block in the OMAP4+ processor that contains at least one TILER instance. TILER, or Tiling and Isometric Lightweight Engine for Rotation, provides IOMMU capabilities through the use of a physical address translation table. The TILER also provides zero cost rotation and mirroring. The TILER provides both 1D and 2D access by providing different views or address ranges that can be used to access the physical memory that has been mapped in through the PAT. Access to the 1D view results in linear access to the underlying memory. Access to the 2D views result in tiled access to the underlying memory resulted in increased efficiency. The TILER address space is managed by a tiler container manager (TCM) and allocates the address space through the use of the Simple Tiler Allocation algorithm (SiTA). The purpose of the algorithm is to keep fragmentation of the address space as low as possible. Signed-off-by: Andy Gross <andy.gross@ti.com> Signed-off-by: Rob Clark <rob@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
124 lines
4.1 KiB
C
124 lines
4.1 KiB
C
/*
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* include/drm/omap_drm.h
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*
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* Copyright (C) 2011 Texas Instruments
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* Author: Rob Clark <rob@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __OMAP_DRM_H__
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#define __OMAP_DRM_H__
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#include <drm/drm.h>
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints.
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*/
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#define OMAP_PARAM_CHIPSET_ID 1 /* ie. 0x3430, 0x4430, etc */
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struct drm_omap_param {
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uint64_t param; /* in */
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uint64_t value; /* in (set_param), out (get_param) */
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};
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#define OMAP_BO_SCANOUT 0x00000001 /* scanout capable (phys contiguous) */
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#define OMAP_BO_CACHE_MASK 0x00000006 /* cache type mask, see cache modes */
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#define OMAP_BO_TILED_MASK 0x00000f00 /* tiled mapping mask, see tiled modes */
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/* cache modes */
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#define OMAP_BO_CACHED 0x00000000 /* default */
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#define OMAP_BO_WC 0x00000002 /* write-combine */
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#define OMAP_BO_UNCACHED 0x00000004 /* strongly-ordered (uncached) */
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/* tiled modes */
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#define OMAP_BO_TILED_8 0x00000100
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#define OMAP_BO_TILED_16 0x00000200
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#define OMAP_BO_TILED_32 0x00000300
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#define OMAP_BO_TILED (OMAP_BO_TILED_8 | OMAP_BO_TILED_16 | OMAP_BO_TILED_32)
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union omap_gem_size {
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uint32_t bytes; /* (for non-tiled formats) */
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struct {
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uint16_t width;
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uint16_t height;
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} tiled; /* (for tiled formats) */
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};
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struct drm_omap_gem_new {
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union omap_gem_size size; /* in */
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uint32_t flags; /* in */
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uint32_t handle; /* out */
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uint32_t __pad;
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};
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/* mask of operations: */
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enum omap_gem_op {
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OMAP_GEM_READ = 0x01,
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OMAP_GEM_WRITE = 0x02,
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};
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struct drm_omap_gem_cpu_prep {
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uint32_t handle; /* buffer handle (in) */
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uint32_t op; /* mask of omap_gem_op (in) */
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};
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struct drm_omap_gem_cpu_fini {
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uint32_t handle; /* buffer handle (in) */
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uint32_t op; /* mask of omap_gem_op (in) */
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/* TODO maybe here we pass down info about what regions are touched
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* by sw so we can be clever about cache ops? For now a placeholder,
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* set to zero and we just do full buffer flush..
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*/
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uint32_t nregions;
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uint32_t __pad;
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};
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struct drm_omap_gem_info {
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uint32_t handle; /* buffer handle (in) */
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uint32_t pad;
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uint64_t offset; /* mmap offset (out) */
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/* note: in case of tiled buffers, the user virtual size can be
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* different from the physical size (ie. how many pages are needed
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* to back the object) which is returned in DRM_IOCTL_GEM_OPEN..
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* This size here is the one that should be used if you want to
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* mmap() the buffer:
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*/
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uint32_t size; /* virtual size for mmap'ing (out) */
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uint32_t __pad;
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};
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#define DRM_OMAP_GET_PARAM 0x00
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#define DRM_OMAP_SET_PARAM 0x01
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/* placeholder for plugin-api
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#define DRM_OMAP_GET_BASE 0x02
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*/
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#define DRM_OMAP_GEM_NEW 0x03
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#define DRM_OMAP_GEM_CPU_PREP 0x04
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#define DRM_OMAP_GEM_CPU_FINI 0x05
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#define DRM_OMAP_GEM_INFO 0x06
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#define DRM_OMAP_NUM_IOCTLS 0x07
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#define DRM_IOCTL_OMAP_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_PARAM, struct drm_omap_param)
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#define DRM_IOCTL_OMAP_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_SET_PARAM, struct drm_omap_param)
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/* placeholder for plugin-api
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#define DRM_IOCTL_OMAP_GET_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GET_BASE, struct drm_omap_get_base)
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*/
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#define DRM_IOCTL_OMAP_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_NEW, struct drm_omap_gem_new)
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#define DRM_IOCTL_OMAP_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_PREP, struct drm_omap_gem_cpu_prep)
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#define DRM_IOCTL_OMAP_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_OMAP_GEM_CPU_FINI, struct drm_omap_gem_cpu_fini)
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#define DRM_IOCTL_OMAP_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_OMAP_GEM_INFO, struct drm_omap_gem_info)
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#endif /* __OMAP_DRM_H__ */
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