7ada90eb9c
msm-next: - OCMEM support for a3xx and a4xx GPUs. - a510 support + display support core: - mst payload deletion fix i915: - uapi alignment fix - fix for power usage regression due to security fixes - change default preemption timeout to 640ms from 100ms - EHL voltage level display fixes - TGL DGL PHY fix - gvt - MI_ATOMIC cmd parser fix, CFL non-priv warning - CI spotted deadlock fix - EHL port D programming fix amdgpu: - VRAM lost fixes on BACO for CI/VI - navi14 DC fixes - misc SR-IOV, gfx10 fixes - XGMI fixes for arcturus - SRIOV fixes amdkfd: - KFD on ppc64le enabled - page table optimisations radeon: - fix for r1xx/2xx register checker. tegra: - displayport regression fixes - DMA API regression fixes mgag200: - fix devices that can't scanout except at 0 addr omap: - fix dma_addr refcounting -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJd6cqnAAoJEAx081l5xIa+YR0P/A0LkilEbSnF/k7zKDjm0HN8 JGsf9ZfQRGA2y8URoLRtNdFjZfyuTSpiDSxsbDI0ShBhRimGHyCSxAJXO42vp8q3 jE57jBoaTSiGtagSO3nxrc1vQP7CfUpaggC2ilKSmcVvTrlqip6iPx7s2PoNyQYc GRVUhkcylnZK5UrMiE8Yz/iNcy3Mh0X8bJQKXMEYxpW2KA3SL4qxuRlYIxXEoMyB 4MlWEV09wHTduf1uYuKdusHjILgR5EiVOdmbvpM92obqZOTokt5/S20TEdhFqiy0 0IHxuEkgVx+trXzGFbmqgh2I7BZvZIbKVCSnBT4AXAvUEJ99kGTdEP0I6uOp2lsC 1DCm+7/hcI8BlwmwC9N6ogUwoAzKn7DNc1urcet/0QVbnZLZlueUK/6fSgUNnUYe miOeMNBmfHr83b75MpnNxYVoyz5S+/DFbtUplYKqxgjDYfiWWceSSE47NB+IHAiI RVpz3AxGpKaw4/w5l2q8VuToWZxdO85TNjgVCTmKfwlYjIbEuveWpZNFqO/GHMm9 x50f4ZYVOjU2TEPnLQNTIJOgv71JrTpoAdFzPVwCeWUf4h4Y4lVLgTLvdG1JLcw+ k9BrA5z2R0kjzPtabRhS6WfSjpgSbY3DgY9hfi+HIUmKvZq4fdtAbBlp1oGSXJ9N zkVrs9eE6Ahkcndi6ZV9 =3cs2 -----END PGP SIGNATURE----- Merge tag 'drm-next-2019-12-06' of git://anongit.freedesktop.org/drm/drm Pull more drm updates from Dave Airlie: "Rob pointed out I missed his pull request for msm-next, it's been in next for a while outside of my tree so shouldn't cause any unexpected issues, it has some OCMEM support in drivers/soc that is acked by other maintainers as it's outside my tree. Otherwise it's a usual fixes pull, i915, amdgpu, the main ones, with some tegra, omap, mgag200 and one core fix. Summary: msm-next: - OCMEM support for a3xx and a4xx GPUs. - a510 support + display support core: - mst payload deletion fix i915: - uapi alignment fix - fix for power usage regression due to security fixes - change default preemption timeout to 640ms from 100ms - EHL voltage level display fixes - TGL DGL PHY fix - gvt - MI_ATOMIC cmd parser fix, CFL non-priv warning - CI spotted deadlock fix - EHL port D programming fix amdgpu: - VRAM lost fixes on BACO for CI/VI - navi14 DC fixes - misc SR-IOV, gfx10 fixes - XGMI fixes for arcturus - SRIOV fixes amdkfd: - KFD on ppc64le enabled - page table optimisations radeon: - fix for r1xx/2xx register checker. tegra: - displayport regression fixes - DMA API regression fixes mgag200: - fix devices that can't scanout except at 0 addr omap: - fix dma_addr refcounting" * tag 'drm-next-2019-12-06' of git://anongit.freedesktop.org/drm/drm: (100 commits) drm/dp_mst: Correct the bug in drm_dp_update_payload_part1() drm/omap: fix dma_addr refcounting drm/tegra: Run hub cleanup on ->remove() drm/tegra: sor: Make the +5V HDMI supply optional drm/tegra: Silence expected errors on IOMMU attach drm/tegra: vic: Export module device table drm/tegra: sor: Implement system suspend/resume drm/tegra: Use proper IOVA address for cursor image drm/tegra: gem: Remove premature import restrictions drm/tegra: gem: Properly pin imported buffers drm/tegra: hub: Remove bogus connection mutex check ia64: agp: Replace empty define with do while agp: Add bridge parameter documentation agp: remove unused variable num_segments agp: move AGPGART_MINOR to include/linux/miscdevice.h agp: remove unused variable size in agp_generic_create_gatt_table drm/dp_mst: Fix build on systems with STACKTRACE_SUPPORT=n drm/radeon: fix r1xx/r2xx register checker for POT textures drm/amdgpu: fix GFX10 missing CSIB set(v3) drm/amdgpu: should stop GFX ring in hw_fini ...
119 lines
4 KiB
C
119 lines
4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
|
|
*/
|
|
#ifndef __QCOM_SCM_INT_H
|
|
#define __QCOM_SCM_INT_H
|
|
|
|
#define QCOM_SCM_SVC_BOOT 0x1
|
|
#define QCOM_SCM_BOOT_ADDR 0x1
|
|
#define QCOM_SCM_SET_DLOAD_MODE 0x10
|
|
#define QCOM_SCM_BOOT_ADDR_MC 0x11
|
|
#define QCOM_SCM_SET_REMOTE_STATE 0xa
|
|
extern int __qcom_scm_set_remote_state(struct device *dev, u32 state, u32 id);
|
|
extern int __qcom_scm_set_dload_mode(struct device *dev, bool enable);
|
|
|
|
#define QCOM_SCM_FLAG_HLOS 0x01
|
|
#define QCOM_SCM_FLAG_COLDBOOT_MC 0x02
|
|
#define QCOM_SCM_FLAG_WARMBOOT_MC 0x04
|
|
extern int __qcom_scm_set_warm_boot_addr(struct device *dev, void *entry,
|
|
const cpumask_t *cpus);
|
|
extern int __qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
|
|
|
|
#define QCOM_SCM_CMD_TERMINATE_PC 0x2
|
|
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
|
#define QCOM_SCM_CMD_CORE_HOTPLUGGED 0x10
|
|
extern void __qcom_scm_cpu_power_down(u32 flags);
|
|
|
|
#define QCOM_SCM_SVC_IO 0x5
|
|
#define QCOM_SCM_IO_READ 0x1
|
|
#define QCOM_SCM_IO_WRITE 0x2
|
|
extern int __qcom_scm_io_readl(struct device *dev, phys_addr_t addr, unsigned int *val);
|
|
extern int __qcom_scm_io_writel(struct device *dev, phys_addr_t addr, unsigned int val);
|
|
|
|
#define QCOM_SCM_SVC_INFO 0x6
|
|
#define QCOM_IS_CALL_AVAIL_CMD 0x1
|
|
extern int __qcom_scm_is_call_available(struct device *dev, u32 svc_id,
|
|
u32 cmd_id);
|
|
|
|
#define QCOM_SCM_SVC_HDCP 0x11
|
|
#define QCOM_SCM_CMD_HDCP 0x01
|
|
extern int __qcom_scm_hdcp_req(struct device *dev,
|
|
struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
|
|
|
|
extern void __qcom_scm_init(void);
|
|
|
|
#define QCOM_SCM_OCMEM_SVC 0xf
|
|
#define QCOM_SCM_OCMEM_LOCK_CMD 0x1
|
|
#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x2
|
|
|
|
extern int __qcom_scm_ocmem_lock(struct device *dev, u32 id, u32 offset,
|
|
u32 size, u32 mode);
|
|
extern int __qcom_scm_ocmem_unlock(struct device *dev, u32 id, u32 offset,
|
|
u32 size);
|
|
|
|
#define QCOM_SCM_SVC_PIL 0x2
|
|
#define QCOM_SCM_PAS_INIT_IMAGE_CMD 0x1
|
|
#define QCOM_SCM_PAS_MEM_SETUP_CMD 0x2
|
|
#define QCOM_SCM_PAS_AUTH_AND_RESET_CMD 0x5
|
|
#define QCOM_SCM_PAS_SHUTDOWN_CMD 0x6
|
|
#define QCOM_SCM_PAS_IS_SUPPORTED_CMD 0x7
|
|
#define QCOM_SCM_PAS_MSS_RESET 0xa
|
|
extern bool __qcom_scm_pas_supported(struct device *dev, u32 peripheral);
|
|
extern int __qcom_scm_pas_init_image(struct device *dev, u32 peripheral,
|
|
dma_addr_t metadata_phys);
|
|
extern int __qcom_scm_pas_mem_setup(struct device *dev, u32 peripheral,
|
|
phys_addr_t addr, phys_addr_t size);
|
|
extern int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 peripheral);
|
|
extern int __qcom_scm_pas_shutdown(struct device *dev, u32 peripheral);
|
|
extern int __qcom_scm_pas_mss_reset(struct device *dev, bool reset);
|
|
|
|
/* common error codes */
|
|
#define QCOM_SCM_V2_EBUSY -12
|
|
#define QCOM_SCM_ENOMEM -5
|
|
#define QCOM_SCM_EOPNOTSUPP -4
|
|
#define QCOM_SCM_EINVAL_ADDR -3
|
|
#define QCOM_SCM_EINVAL_ARG -2
|
|
#define QCOM_SCM_ERROR -1
|
|
#define QCOM_SCM_INTERRUPTED 1
|
|
|
|
static inline int qcom_scm_remap_error(int err)
|
|
{
|
|
switch (err) {
|
|
case QCOM_SCM_ERROR:
|
|
return -EIO;
|
|
case QCOM_SCM_EINVAL_ADDR:
|
|
case QCOM_SCM_EINVAL_ARG:
|
|
return -EINVAL;
|
|
case QCOM_SCM_EOPNOTSUPP:
|
|
return -EOPNOTSUPP;
|
|
case QCOM_SCM_ENOMEM:
|
|
return -ENOMEM;
|
|
case QCOM_SCM_V2_EBUSY:
|
|
return -EBUSY;
|
|
}
|
|
return -EINVAL;
|
|
}
|
|
|
|
#define QCOM_SCM_SVC_MP 0xc
|
|
#define QCOM_SCM_RESTORE_SEC_CFG 2
|
|
extern int __qcom_scm_restore_sec_cfg(struct device *dev, u32 device_id,
|
|
u32 spare);
|
|
#define QCOM_SCM_IOMMU_SECURE_PTBL_SIZE 3
|
|
#define QCOM_SCM_IOMMU_SECURE_PTBL_INIT 4
|
|
#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
|
|
#define QCOM_SCM_CONFIG_ERRATA1 0x3
|
|
#define QCOM_SCM_CONFIG_ERRATA1_CLIENT_ALL 0x2
|
|
extern int __qcom_scm_iommu_secure_ptbl_size(struct device *dev, u32 spare,
|
|
size_t *size);
|
|
extern int __qcom_scm_iommu_secure_ptbl_init(struct device *dev, u64 addr,
|
|
u32 size, u32 spare);
|
|
extern int __qcom_scm_qsmmu500_wait_safe_toggle(struct device *dev,
|
|
bool enable);
|
|
#define QCOM_MEM_PROT_ASSIGN_ID 0x16
|
|
extern int __qcom_scm_assign_mem(struct device *dev,
|
|
phys_addr_t mem_region, size_t mem_sz,
|
|
phys_addr_t src, size_t src_sz,
|
|
phys_addr_t dest, size_t dest_sz);
|
|
|
|
#endif
|