2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
70 lines
2.3 KiB
C
70 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Exynos Specific Extensions for Synopsys DW Multimedia Card Interface driver
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*
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* Copyright (C) 2012-2014 Samsung Electronics Co., Ltd.
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*/
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#ifndef _DW_MMC_EXYNOS_H_
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#define _DW_MMC_EXYNOS_H_
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#define SDMMC_CLKSEL 0x09C
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#define SDMMC_CLKSEL64 0x0A8
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/* Extended Register's Offset */
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#define SDMMC_HS400_DQS_EN 0x180
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#define SDMMC_HS400_ASYNC_FIFO_CTRL 0x184
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#define SDMMC_HS400_DLINE_CTRL 0x188
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/* CLKSEL register defines */
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#define SDMMC_CLKSEL_CCLK_SAMPLE(x) (((x) & 7) << 0)
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#define SDMMC_CLKSEL_CCLK_DRIVE(x) (((x) & 7) << 16)
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#define SDMMC_CLKSEL_CCLK_DIVIDER(x) (((x) & 7) << 24)
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#define SDMMC_CLKSEL_GET_DRV_WD3(x) (((x) >> 16) & 0x7)
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#define SDMMC_CLKSEL_GET_DIV(x) (((x) >> 24) & 0x7)
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#define SDMMC_CLKSEL_UP_SAMPLE(x, y) (((x) & ~SDMMC_CLKSEL_CCLK_SAMPLE(7)) |\
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SDMMC_CLKSEL_CCLK_SAMPLE(y))
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#define SDMMC_CLKSEL_TIMING(x, y, z) (SDMMC_CLKSEL_CCLK_SAMPLE(x) | \
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SDMMC_CLKSEL_CCLK_DRIVE(y) | \
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SDMMC_CLKSEL_CCLK_DIVIDER(z))
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#define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7)
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#define SDMMC_CLKSEL_WAKEUP_INT BIT(11)
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/* RCLK_EN register defines */
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#define DATA_STROBE_EN BIT(0)
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#define AXI_NON_BLOCKING_WR BIT(7)
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/* DLINE_CTRL register defines */
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#define DQS_CTRL_RD_DELAY(x, y) (((x) & ~0x3FF) | ((y) & 0x3FF))
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#define DQS_CTRL_GET_RD_DELAY(x) ((x) & 0x3FF)
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/* Protector Register */
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#define SDMMC_EMMCP_BASE 0x1000
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#define SDMMC_MPSECURITY (SDMMC_EMMCP_BASE + 0x0010)
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#define SDMMC_MPSBEGIN0 (SDMMC_EMMCP_BASE + 0x0200)
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#define SDMMC_MPSEND0 (SDMMC_EMMCP_BASE + 0x0204)
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#define SDMMC_MPSCTRL0 (SDMMC_EMMCP_BASE + 0x020C)
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/* SMU control defines */
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#define SDMMC_MPSCTRL_SECURE_READ_BIT BIT(7)
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#define SDMMC_MPSCTRL_SECURE_WRITE_BIT BIT(6)
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#define SDMMC_MPSCTRL_NON_SECURE_READ_BIT BIT(5)
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#define SDMMC_MPSCTRL_NON_SECURE_WRITE_BIT BIT(4)
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#define SDMMC_MPSCTRL_USE_FUSE_KEY BIT(3)
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#define SDMMC_MPSCTRL_ECB_MODE BIT(2)
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#define SDMMC_MPSCTRL_ENCRYPTION BIT(1)
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#define SDMMC_MPSCTRL_VALID BIT(0)
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/* Maximum number of Ending sector */
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#define SDMMC_ENDING_SEC_NR_MAX 0xFFFFFFFF
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/* Fixed clock divider */
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#define EXYNOS4210_FIXED_CIU_CLK_DIV 2
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#define EXYNOS4412_FIXED_CIU_CLK_DIV 4
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#define HS400_FIXED_CIU_CLK_DIV 1
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/* Minimal required clock frequency for cclkin, unit: HZ */
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#define EXYNOS_CCLKIN_MIN 50000000
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#endif /* _DW_MMC_EXYNOS_H_ */
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