![André Goddard Rosa](/assets/img/avatar_default.png)
Signed-off-by: André Goddard Rosa <andre.goddard@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
445 lines
11 KiB
C
445 lines
11 KiB
C
#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/fs.h>
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#include <linux/cdev.h>
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#include <linux/kdev_t.h>
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#include <linux/semaphore.h>
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#include <linux/mm.h>
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#include <linux/poll.h>
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#include <linux/wait.h>
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#include <linux/ioctl.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/pagemap.h>
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#include <linux/pci.h>
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#include <linux/firmware.h>
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#include <linux/sched.h>
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#include "rar_driver.h"
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/* The following defines are for the IPC process to retrieve RAR in */
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/* === Lincroft Message Bus Interface === */
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/* Message Control Register */
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#define LNC_MCR_OFFSET 0xD0
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/* Message Data Register */
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#define LNC_MDR_OFFSET 0xD4
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/* Message Opcodes */
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#define LNC_MESSAGE_READ_OPCODE 0xD0
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#define LNC_MESSAGE_WRITE_OPCODE 0xE0
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/* Message Write Byte Enables */
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#define LNC_MESSAGE_BYTE_WRITE_ENABLES 0xF
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/* B-unit Port */
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#define LNC_BUNIT_PORT 0x3
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/* === Lincroft B-Unit Registers - Programmed by IA32 firmware === */
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#define LNC_BRAR0L 0x10
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#define LNC_BRAR0H 0x11
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#define LNC_BRAR1L 0x12
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#define LNC_BRAR1H 0x13
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/* Reserved for SeP */
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#define LNC_BRAR2L 0x14
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#define LNC_BRAR2H 0x15
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/* This structure is only used during module initialization. */
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struct RAR_offsets {
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int low; /* Register offset for low RAR physical address. */
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int high; /* Register offset for high RAR physical address. */
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};
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struct pci_dev *rar_dev;
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static uint32_t registered;
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/* Moorestown supports three restricted access regions. */
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#define MRST_NUM_RAR 3
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struct RAR_address_struct rar_addr[MRST_NUM_RAR];
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/* prototype for init */
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static int __init rar_init_handler(void);
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static void __exit rar_exit_handler(void);
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/*
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function that is activated on the successfull probe of the RAR device
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*/
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static int __devinit rar_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
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static struct pci_device_id rar_pci_id_tbl[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4110) },
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{ 0 }
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};
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MODULE_DEVICE_TABLE(pci, rar_pci_id_tbl);
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/* field for registering driver to PCI device */
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static struct pci_driver rar_pci_driver = {
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.name = "rar_driver",
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.id_table = rar_pci_id_tbl,
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.probe = rar_probe
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};
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/* This function is used to retrieved RAR info using the IPC message
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bus interface */
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static int memrar_get_rar_addr(struct pci_dev* pdev,
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int offset,
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u32 *addr)
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{
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/*
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* ======== The Lincroft Message Bus Interface ========
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* Lincroft registers may be obtained from the PCI
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* (the Host Bridge) using the Lincroft Message Bus
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* Interface. That message bus interface is generally
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* comprised of two registers: a control register (MCR, 0xDO)
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* and a data register (MDR, 0xD4).
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*
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* The MCR (message control register) format is the following:
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* 1. [31:24]: Opcode
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* 2. [23:16]: Port
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* 3. [15:8]: Register Offset
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* 4. [7:4]: Byte Enables (use 0xF to set all of these bits
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* to 1)
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* 5. [3:0]: reserved
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*
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* Read (0xD0) and write (0xE0) opcodes are written to the
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* control register when reading and writing to Lincroft
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* registers, respectively.
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*
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* We're interested in registers found in the Lincroft
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* B-unit. The B-unit port is 0x3.
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*
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* The six B-unit RAR register offsets we use are listed
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* earlier in this file.
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*
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* Lastly writing to the MCR register requires the "Byte
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* enables" bits to be set to 1. This may be achieved by
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* writing 0xF at bit 4.
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*
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* The MDR (message data register) format is the following:
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* 1. [31:0]: Read/Write Data
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*
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* Data being read from this register is only available after
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* writing the appropriate control message to the MCR
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* register.
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*
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* Data being written to this register must be written before
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* writing the appropriate control message to the MCR
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* register.
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*/
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int result = 0; /* result */
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/* Construct control message */
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u32 const message =
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(LNC_MESSAGE_READ_OPCODE << 24)
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| (LNC_BUNIT_PORT << 16)
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| (offset << 8)
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| (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4);
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printk(KERN_WARNING "rar- offset to LNC MSG is %x\n",offset);
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if (addr == 0)
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return -EINVAL;
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/* Send the control message */
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result = pci_write_config_dword(pdev,
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LNC_MCR_OFFSET,
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message);
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printk(KERN_WARNING "rar- result from send ctl register is %x\n"
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,result);
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if (!result)
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result = pci_read_config_dword(pdev,
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LNC_MDR_OFFSET,
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addr);
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printk(KERN_WARNING "rar- result from read data register is %x\n",
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result);
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printk(KERN_WARNING "rar- value read from data register is %x\n",
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*addr);
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if (result)
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return -1;
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else
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return 0;
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}
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static int memrar_set_rar_addr(struct pci_dev* pdev,
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int offset,
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u32 addr)
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{
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/*
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* ======== The Lincroft Message Bus Interface ========
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* Lincroft registers may be obtained from the PCI
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* (the Host Bridge) using the Lincroft Message Bus
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* Interface. That message bus interface is generally
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* comprised of two registers: a control register (MCR, 0xDO)
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* and a data register (MDR, 0xD4).
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*
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* The MCR (message control register) format is the following:
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* 1. [31:24]: Opcode
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* 2. [23:16]: Port
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* 3. [15:8]: Register Offset
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* 4. [7:4]: Byte Enables (use 0xF to set all of these bits
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* to 1)
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* 5. [3:0]: reserved
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*
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* Read (0xD0) and write (0xE0) opcodes are written to the
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* control register when reading and writing to Lincroft
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* registers, respectively.
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*
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* We're interested in registers found in the Lincroft
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* B-unit. The B-unit port is 0x3.
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*
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* The six B-unit RAR register offsets we use are listed
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* earlier in this file.
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*
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* Lastly writing to the MCR register requires the "Byte
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* enables" bits to be set to 1. This may be achieved by
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* writing 0xF at bit 4.
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*
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* The MDR (message data register) format is the following:
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* 1. [31:0]: Read/Write Data
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*
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* Data being read from this register is only available after
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* writing the appropriate control message to the MCR
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* register.
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*
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* Data being written to this register must be written before
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* writing the appropriate control message to the MCR
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* register.
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*/
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int result = 0; /* result */
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/* Construct control message */
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u32 const message =
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(LNC_MESSAGE_WRITE_OPCODE << 24)
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| (LNC_BUNIT_PORT << 16)
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| (offset << 8)
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| (LNC_MESSAGE_BYTE_WRITE_ENABLES << 4);
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printk(KERN_WARNING "rar- offset to LNC MSG is %x\n",offset);
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if (addr == 0)
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return -EINVAL;
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/* Send the control message */
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result = pci_write_config_dword(pdev,
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LNC_MDR_OFFSET,
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addr);
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printk(KERN_WARNING "rar- result from send ctl register is %x\n"
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,result);
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if (!result)
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result = pci_write_config_dword(pdev,
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LNC_MCR_OFFSET,
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message);
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printk(KERN_WARNING "rar- result from write data register is %x\n",
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result);
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printk(KERN_WARNING "rar- value read to data register is %x\n",
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addr);
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if (result)
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return -1;
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else
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return 0;
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}
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/*
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* Initialize RAR parameters, such as physical addresses, etc.
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*/
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static int memrar_init_rar_params(struct pci_dev *pdev)
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{
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struct RAR_offsets const offsets[] = {
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{ LNC_BRAR0L, LNC_BRAR0H },
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{ LNC_BRAR1L, LNC_BRAR1H },
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{ LNC_BRAR2L, LNC_BRAR2H }
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};
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size_t const num_offsets = sizeof(offsets) / sizeof(offsets[0]);
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struct RAR_offsets const *end = offsets + num_offsets;
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struct RAR_offsets const *i;
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unsigned int n = 0;
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int result = 0;
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/* Retrieve RAR start and end physical addresses. */
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/*
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* Access the RAR registers through the Lincroft Message Bus
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* Interface on PCI device: 00:00.0 Host bridge.
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*/
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/* struct pci_dev *pdev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0)); */
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if (pdev == NULL)
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return -ENODEV;
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for (i = offsets; i != end; ++i, ++n) {
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if (memrar_get_rar_addr (pdev,
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(*i).low,
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&(rar_addr[n].low)) != 0
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|| memrar_get_rar_addr (pdev,
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(*i).high,
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&(rar_addr[n].high)) != 0) {
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result = -1;
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break;
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}
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}
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/* Done accessing the device. */
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/* pci_dev_put(pdev); */
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if (result == 0) {
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if(1) {
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size_t z;
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for (z = 0; z != MRST_NUM_RAR; ++z) {
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printk(KERN_WARNING "rar - BRAR[%Zd] physical address low\n"
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"\tlow: 0x%08x\n"
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"\thigh: 0x%08x\n",
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z,
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rar_addr[z].low,
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rar_addr[z].high);
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}
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}
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}
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return result;
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}
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/*
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function that is activated on the successfull probe of the RAR device
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*/
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static int __devinit rar_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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/* error */
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int error;
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/*------------------------
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CODE
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---------------------------*/
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DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED,
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"Rar pci probe starting\n");
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error = 0;
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/* enable the device */
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error = pci_enable_device(pdev);
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if (error) {
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DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED,
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"error enabling pci device\n");
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goto end_function;
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}
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rar_dev = pdev;
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registered = 1;
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/* Initialize the RAR parameters, which have to be retrieved */
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/* via the message bus service */
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error=memrar_init_rar_params(rar_dev);
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if (error) {
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DEBUG_PRINT_0(RAR_DEBUG_LEVEL_EXTENDED,
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"error getting RAR addresses device\n");
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registered = 0;
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goto end_function;
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}
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end_function:
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return error;
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}
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/*
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this function registers th driver to
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the device subsystem( either PCI, USB, etc)
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*/
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static int __init rar_init_handler(void)
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{
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return pci_register_driver(&rar_pci_driver);
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}
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static void __exit rar_exit_handler(void)
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{
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pci_unregister_driver(&rar_pci_driver);
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}
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module_init(rar_init_handler);
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module_exit(rar_exit_handler);
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MODULE_LICENSE("GPL");
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/* The get_rar_address function is used by other device drivers
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* to obtain RAR address information on a RAR. It takes two
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* parameter:
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*
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* int rar_index
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* The rar_index is an index to the rar for which you wish to retrieve
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* the address information.
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* Values can be 0,1, or 2.
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*
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* struct RAR_address_struct is a pointer to a place to which the function
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* can return the address structure for the RAR.
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*
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* The function returns a 0 upon success or a -1 if there is no RAR
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* facility on this system.
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*/
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int get_rar_address(int rar_index,struct RAR_address_struct *addresses)
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{
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if (registered && (rar_index < 3) && (rar_index >= 0)) {
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*addresses=rar_addr[rar_index];
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/* strip off lock bit information */
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addresses->low = addresses->low & 0xfffffff0;
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addresses->high = addresses->high & 0xfffffff0;
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return 0;
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}
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else {
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return -ENODEV;
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}
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}
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EXPORT_SYMBOL(get_rar_address);
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/* The lock_rar function is ued by other device drivers to lock an RAR.
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* once an RAR is locked, it stays locked until the next system reboot.
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* The function takes one parameter:
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*
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* int rar_index
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* The rar_index is an index to the rar that you want to lock.
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* Values can be 0,1, or 2.
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*
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* The function returns a 0 upon success or a -1 if there is no RAR
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* facility on this system.
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*/
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int lock_rar(int rar_index)
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{
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u32 working_addr;
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int result;
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if (registered && (rar_index < 3) && (rar_index >= 0)) {
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/* first make sure that lock bits are clear (this does lock) */
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working_addr=rar_addr[rar_index].low & 0xfffffff0;
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/* now send that value to the register using the IPC */
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result=memrar_set_rar_addr(rar_dev,rar_index,working_addr);
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return result;
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}
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else {
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return -ENODEV;
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}
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}
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