2f3428b5cf
The Exynos542x SoCs using A15+A7 can boot to A15 or A7. If it boots using A7 (like on Odroid XU family boards), it can't choose right UART physical address only the part number of CP15. Fix the detection logic by checking the Cluster ID additionally. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Tested-by: Marek Szyprowski <m.szyprowski@samsung.com> [k.kozlowski: Extend commit message] Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
44 lines
1.3 KiB
ArmAsm
44 lines
1.3 KiB
ArmAsm
/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/* pull in the relevant register and map files. */
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#define S3C_ADDR_BASE 0xF6000000
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#define S3C_VA_UART S3C_ADDR_BASE + 0x01000000
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#define EXYNOS4_PA_UART 0x13800000
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#define EXYNOS5_PA_UART 0x12C00000
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/* note, for the boot process to work we have to keep the UART
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* virtual address aligned to an 1MiB boundary for the L1
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* mapping the head code makes. We keep the UART virtual address
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* aligned and add in the offset when we load the value here.
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*/
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.macro addruart, rp, rv, tmp
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mrc p15, 0, \tmp, c0, c0, 0
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and \tmp, \tmp, #0xf0
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teq \tmp, #0xf0 @@ A15
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beq 100f
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mrc p15, 0, \tmp, c0, c0, 5
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and \tmp, \tmp, #0xf00
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teq \tmp, #0x100 @@ A15 + A7 but boot to A7
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100: ldreq \rp, =EXYNOS5_PA_UART
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movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
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ldr \rv, =S3C_VA_UART
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#if CONFIG_DEBUG_S3C_UART != 0
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add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
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add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
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#endif
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.endm
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#define fifo_full fifo_full_s5pv210
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#define fifo_level fifo_level_s5pv210
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#include <debug/samsung.S>
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