dabd145692
This patch moves pad retention control from S5PV210 machine code to Exynos pin controller driver. This helps to avoid possible ordering and logical dependencies between machine and pin control code. Till now it worked fine only because sys_ops for machine code and pin controller were called in registration order. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Tomasz Figa <tomasz.figa@gmail.com> For mach-s5pv210: Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
198 lines
6.5 KiB
C
198 lines
6.5 KiB
C
/*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com/
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*
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* S5PV210 - Clock register definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_REGS_CLOCK_H
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#define __ASM_ARCH_REGS_CLOCK_H __FILE__
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#include <plat/map-base.h>
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#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
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#define S5P_APLL_LOCK S5P_CLKREG(0x00)
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#define S5P_MPLL_LOCK S5P_CLKREG(0x08)
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#define S5P_EPLL_LOCK S5P_CLKREG(0x10)
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#define S5P_VPLL_LOCK S5P_CLKREG(0x20)
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#define S5P_APLL_CON S5P_CLKREG(0x100)
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#define S5P_MPLL_CON S5P_CLKREG(0x108)
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#define S5P_EPLL_CON S5P_CLKREG(0x110)
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#define S5P_EPLL_CON1 S5P_CLKREG(0x114)
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#define S5P_VPLL_CON S5P_CLKREG(0x120)
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#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
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#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
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#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
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#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
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#define S5P_CLK_SRC4 S5P_CLKREG(0x210)
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#define S5P_CLK_SRC5 S5P_CLKREG(0x214)
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#define S5P_CLK_SRC6 S5P_CLKREG(0x218)
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#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280)
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#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284)
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#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
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#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
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#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
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#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
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#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
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#define S5P_CLK_DIV5 S5P_CLKREG(0x314)
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#define S5P_CLK_DIV6 S5P_CLKREG(0x318)
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#define S5P_CLK_DIV7 S5P_CLKREG(0x31C)
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#define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x400)
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#define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x404)
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#define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x408)
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#define S5P_CLKGATE_PERI0 S5P_CLKREG(0x420)
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#define S5P_CLKGATE_PERI1 S5P_CLKREG(0x424)
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#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x440)
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#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x444)
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#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460)
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#define S5P_CLKGATE_IP1 S5P_CLKREG(0x464)
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#define S5P_CLKGATE_IP2 S5P_CLKREG(0x468)
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#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C)
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#define S5P_CLKGATE_IP4 S5P_CLKREG(0x470)
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#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480)
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#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484)
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#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488)
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#define S5P_CLK_OUT S5P_CLKREG(0x500)
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/* DIV/MUX STATUS */
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#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000)
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#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004)
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#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100)
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#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104)
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/* CLKSRC0 */
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#define S5P_CLKSRC0_MUX200_SHIFT (16)
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#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
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#define S5P_CLKSRC0_MUX166_MASK (0x1<<20)
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#define S5P_CLKSRC0_MUX133_MASK (0x1<<24)
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/* CLKSRC2 */
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#define S5P_CLKSRC2_G3D_SHIFT (0)
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#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT)
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#define S5P_CLKSRC2_MFC_SHIFT (4)
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#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT)
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/* CLKSRC6*/
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#define S5P_CLKSRC6_ONEDRAM_SHIFT (24)
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#define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT)
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/* CLKDIV0 */
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#define S5P_CLKDIV0_APLL_SHIFT (0)
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#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT)
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#define S5P_CLKDIV0_A2M_SHIFT (4)
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#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT)
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#define S5P_CLKDIV0_HCLK200_SHIFT (8)
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#define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
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#define S5P_CLKDIV0_PCLK100_SHIFT (12)
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#define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
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#define S5P_CLKDIV0_HCLK166_SHIFT (16)
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#define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT)
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#define S5P_CLKDIV0_PCLK83_SHIFT (20)
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#define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
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#define S5P_CLKDIV0_HCLK133_SHIFT (24)
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#define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT)
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#define S5P_CLKDIV0_PCLK66_SHIFT (28)
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#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
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/* CLKDIV2 */
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#define S5P_CLKDIV2_G3D_SHIFT (0)
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#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT)
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#define S5P_CLKDIV2_MFC_SHIFT (4)
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#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT)
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/* CLKDIV6 */
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#define S5P_CLKDIV6_ONEDRAM_SHIFT (28)
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#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
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#define S5P_SWRESET S5P_CLKREG(0x2000)
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#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100)
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/* Registers related to power management */
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#define S5P_PWR_CFG S5P_CLKREG(0xC000)
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#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004)
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#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008)
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#define S5P_PWR_MODE S5P_CLKREG(0xC00C)
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#define S5P_NORMAL_CFG S5P_CLKREG(0xC010)
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#define S5P_IDLE_CFG S5P_CLKREG(0xC020)
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#define S5P_STOP_CFG S5P_CLKREG(0xC030)
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#define S5P_STOP_MEM_CFG S5P_CLKREG(0xC034)
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#define S5P_SLEEP_CFG S5P_CLKREG(0xC040)
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#define S5P_OSC_FREQ S5P_CLKREG(0xC100)
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#define S5P_OSC_STABLE S5P_CLKREG(0xC104)
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#define S5P_PWR_STABLE S5P_CLKREG(0xC108)
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#define S5P_MTC_STABLE S5P_CLKREG(0xC110)
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#define S5P_CLAMP_STABLE S5P_CLKREG(0xC114)
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#define S5P_WAKEUP_STAT S5P_CLKREG(0xC200)
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#define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204)
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#define S5P_OTHERS S5P_CLKREG(0xE000)
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#define S5P_OM_STAT S5P_CLKREG(0xE100)
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#define S5P_HDMI_PHY_CONTROL S5P_CLKREG(0xE804)
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#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C)
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#define S5P_DAC_PHY_CONTROL S5P_CLKREG(0xE810)
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#define S5P_INFORM0 S5P_CLKREG(0xF000)
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#define S5P_INFORM1 S5P_CLKREG(0xF004)
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#define S5P_INFORM2 S5P_CLKREG(0xF008)
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#define S5P_INFORM3 S5P_CLKREG(0xF00C)
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#define S5P_INFORM4 S5P_CLKREG(0xF010)
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#define S5P_INFORM5 S5P_CLKREG(0xF014)
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#define S5P_INFORM6 S5P_CLKREG(0xF018)
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#define S5P_INFORM7 S5P_CLKREG(0xF01C)
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#define S5P_RST_STAT S5P_CLKREG(0xA000)
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#define S5P_OSC_CON S5P_CLKREG(0x8000)
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#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
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#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200)
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#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204)
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#define S5P_IDLE_CFG_TL_MASK (3 << 30)
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#define S5P_IDLE_CFG_TM_MASK (3 << 28)
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#define S5P_IDLE_CFG_TL_ON (2 << 30)
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#define S5P_IDLE_CFG_TM_ON (2 << 28)
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#define S5P_IDLE_CFG_DIDLE (1 << 0)
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#define S5P_CFG_WFI_CLEAN (~(3 << 8))
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#define S5P_CFG_WFI_IDLE (1 << 8)
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#define S5P_CFG_WFI_STOP (2 << 8)
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#define S5P_CFG_WFI_SLEEP (3 << 8)
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#define S5P_OTHER_SYS_INT 24
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#define S5P_OTHER_STA_TYPE 23
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#define S5P_OTHER_SYSC_INTOFF (1 << 0)
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#define STA_TYPE_EXPON 0
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#define STA_TYPE_SFR 1
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#define S5P_PWR_STA_EXP_SCALE 0
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#define S5P_PWR_STA_CNT 4
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#define S5P_PWR_STABLE_COUNT 85500
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#define S5P_SLEEP_CFG_OSC_EN (1 << 0)
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#define S5P_SLEEP_CFG_USBOSC_EN (1 << 1)
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/* OTHERS Resgister */
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#define S5P_OTHERS_USB_SIG_MASK (1 << 16)
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/* S5P_DAC_CONTROL */
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#define S5P_DAC_ENABLE (1)
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#define S5P_DAC_DISABLE (0)
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#endif /* __ASM_ARCH_REGS_CLOCK_H */
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