b8d56b61af
* Remove stale comment from Kconfig * Consolidate SCU mapping code -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIbBAABAgAGBQJWzQH2AAoJENfPZGlqN0++//kP91uA0cVhvdjTHF6P4EFGFRoe vYEQlzNOVkqeNPd/Vx1VdD6sAXlhQ11rxAzkAtaD1mX6zQlV3cLS+ouxjufuqGg/ Gw0Abjhi7+yIstg0MYb0Q/WZ4yfuscyXf2VKEudiX1p/YSpYKAXA1PRzitO4Vh/V RSo1e0P70WpKlkqwXlOx4USrM50zXsJCX73x4JRQjw82rLuTMNaUXsA4Vl7hI091 FT1tumiQ0TgzO7DLFfMqbSf8YwlzbZeiBrTyp7pmpdWEO7L2vDuk5rGnzpY14eHu TEK2aT+bAK41mFme7rtYic1OG3L4H4zSOBSGpuJNanp+Dw0r4PO9Ro5hgorNBweV 2NY/qv9i5FZQ+5XEdN+vsALDIZXxa0T+c/LMbv8NUsuSXCIxYeJ7EHAaGF809tkh BNxww1aEPc0ak+ClY3NOXgtD7OycVOOIjsUT3Xhj0Pk+aNZSz48qUACBo03NzJR2 6aTIWGvuN/saz4soeYtwMD8Z5SzLiJaLF2ud8msTlVFvP0HCeGztdrdwNQwBzaaS eTS0cMLvjdkEI8mH+5cZ+5g3R/O3XiaPOD7OjwLwAlQNjAdK9IIf0NqNBgqHSVi2 jYU+xAaHrYpd6rSDe8gbS9F86i59++/AmtmdkFy4e3P+5qD58+hVYYCClONm3zAN Z4i09eAjsd3wHCnZPdo= =vtm3 -----END PGP SIGNATURE----- Merge tag 'renesas-cleanup2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/cleanup Merge "Second Round of Renesas ARM Based SoC Cleanup for v4.6" from Simon Horman: * Remove stale comment from Kconfig * Consolidate SCU mapping code * tag 'renesas-cleanup2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Kconfig: Get rid of old comment ARM: shmobile: Consolidate SCU mapping code
41 lines
1.2 KiB
ArmAsm
41 lines
1.2 KiB
ArmAsm
/*
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* Shared SCU setup for mach-shmobile
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*
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* Copyright (C) 2012 Bastian Hecht
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/memory.h>
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/*
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* Boot code for secondary CPUs.
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*
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* First we turn on L1 cache coherency for our CPU. Then we jump to
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* secondary_startup that invalidates the cache and hands over control
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* to the common ARM startup code.
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*/
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ENTRY(shmobile_boot_scu)
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@ r0 = SCU base address
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mrc p15, 0, r1, c0, c0, 5 @ read MPIDR
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and r1, r1, #3 @ mask out cpu ID
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lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
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ldr r2, [r0, #8] @ SCU Power Status Register
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mov r3, #3
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lsl r3, r3, r1
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bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
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str r2, [r0, #8] @ write back
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b secondary_startup
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ENDPROC(shmobile_boot_scu)
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