fcaf20360a
Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
57 lines
1.6 KiB
C
57 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2012 DENX Software Engineering, GmbH
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*
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* Pulled from code:
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* Portions copyright (C) 2003 Russell King, PXA MMCI Driver
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* Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
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*
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* Copyright 2008 Embedded Alley Solutions, Inc.
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/spi/mxs-spi.h>
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void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate)
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{
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unsigned int ssp_clk, ssp_sck;
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u32 clock_divide, clock_rate;
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u32 val;
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ssp_clk = clk_get_rate(ssp->clk);
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for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
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clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
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clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
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if (clock_rate <= 255)
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break;
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}
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if (clock_divide > 254) {
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dev_err(ssp->dev,
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"%s: cannot set clock to %d\n", __func__, rate);
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return;
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}
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ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
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val = readl(ssp->base + HW_SSP_TIMING(ssp));
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val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
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val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
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val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
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writel(val, ssp->base + HW_SSP_TIMING(ssp));
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ssp->clk_rate = ssp_sck;
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dev_dbg(ssp->dev,
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"%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
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__func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
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}
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EXPORT_SYMBOL_GPL(mxs_ssp_set_clk_rate);
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