2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
433 lines
12 KiB
C
433 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Broadcom Starfighter 2 switch register defines
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*
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* Copyright (C) 2014, Broadcom Corporation
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*/
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#ifndef __BCM_SF2_REGS_H
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#define __BCM_SF2_REGS_H
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/* Register set relative to 'REG' */
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enum bcm_sf2_reg_offs {
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REG_SWITCH_CNTRL = 0,
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REG_SWITCH_STATUS,
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REG_DIR_DATA_WRITE,
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REG_DIR_DATA_READ,
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REG_SWITCH_REVISION,
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REG_PHY_REVISION,
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REG_SPHY_CNTRL,
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REG_RGMII_0_CNTRL,
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REG_RGMII_1_CNTRL,
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REG_RGMII_2_CNTRL,
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REG_LED_0_CNTRL,
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REG_LED_1_CNTRL,
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REG_LED_2_CNTRL,
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REG_SWITCH_REG_MAX,
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};
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/* Relative to REG_SWITCH_CNTRL */
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#define MDIO_MASTER_SEL (1 << 0)
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/* Relative to REG_SWITCH_REVISION */
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#define SF2_REV_MASK 0xffff
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#define SWITCH_TOP_REV_SHIFT 16
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#define SWITCH_TOP_REV_MASK 0xffff
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/* Relative to REG_PHY_REVISION */
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#define PHY_REVISION_MASK 0xffff
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/* Relative to REG_SPHY_CNTRL */
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#define IDDQ_BIAS (1 << 0)
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#define EXT_PWR_DOWN (1 << 1)
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#define FORCE_DLL_EN (1 << 2)
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#define IDDQ_GLOBAL_PWR (1 << 3)
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#define CK25_DIS (1 << 4)
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#define PHY_RESET (1 << 5)
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#define PHY_PHYAD_SHIFT 8
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#define PHY_PHYAD_MASK 0x1F
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#define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_CNTRL + (x))
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/* Relative to REG_RGMII_CNTRL */
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#define RGMII_MODE_EN (1 << 0)
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#define ID_MODE_DIS (1 << 1)
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#define PORT_MODE_SHIFT 2
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#define INT_EPHY (0 << PORT_MODE_SHIFT)
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#define INT_GPHY (1 << PORT_MODE_SHIFT)
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#define EXT_EPHY (2 << PORT_MODE_SHIFT)
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#define EXT_GPHY (3 << PORT_MODE_SHIFT)
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#define EXT_REVMII (4 << PORT_MODE_SHIFT)
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#define PORT_MODE_MASK 0x7
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#define RVMII_REF_SEL (1 << 5)
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#define RX_PAUSE_EN (1 << 6)
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#define TX_PAUSE_EN (1 << 7)
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#define TX_CLK_STOP_EN (1 << 8)
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#define LPI_COUNT_SHIFT 9
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#define LPI_COUNT_MASK 0x3F
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#define REG_LED_CNTRL(x) (REG_LED_0_CNTRL + (x))
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#define SPDLNK_SRC_SEL (1 << 24)
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/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
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#define INTRL2_CPU_STATUS 0x00
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#define INTRL2_CPU_SET 0x04
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#define INTRL2_CPU_CLEAR 0x08
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#define INTRL2_CPU_MASK_STATUS 0x0c
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#define INTRL2_CPU_MASK_SET 0x10
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#define INTRL2_CPU_MASK_CLEAR 0x14
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/* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
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#define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
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#define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
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#define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
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#define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
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#define P_GPHY_IRQ(x) (1 << (4 + (x)))
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#define P_NUM_IRQ 5
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#define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
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P_LINK_DOWN_IRQ((x)) | \
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P_ENERGY_ON_IRQ((x)) | \
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P_ENERGY_OFF_IRQ((x)) | \
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P_GPHY_IRQ((x)))
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/* INTRL2_0 interrupt sources */
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#define P0_IRQ_OFF 0
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#define MEM_DOUBLE_IRQ (1 << 5)
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#define EEE_LPI_IRQ (1 << 6)
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#define P5_CPU_WAKE_IRQ (1 << 7)
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#define P8_CPU_WAKE_IRQ (1 << 8)
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#define P7_CPU_WAKE_IRQ (1 << 9)
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#define IEEE1588_IRQ (1 << 10)
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#define MDIO_ERR_IRQ (1 << 11)
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#define MDIO_DONE_IRQ (1 << 12)
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#define GISB_ERR_IRQ (1 << 13)
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#define UBUS_ERR_IRQ (1 << 14)
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#define FAILOVER_ON_IRQ (1 << 15)
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#define FAILOVER_OFF_IRQ (1 << 16)
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#define TCAM_SOFT_ERR_IRQ (1 << 17)
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/* INTRL2_1 interrupt sources */
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#define P7_IRQ_OFF 0
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#define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
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/* Register set relative to 'ACB' */
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#define ACB_CONTROL 0x00
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#define ACB_EN (1 << 0)
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#define ACB_ALGORITHM (1 << 1)
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#define ACB_FLUSH_SHIFT 2
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#define ACB_FLUSH_MASK 0x3
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#define ACB_QUEUE_0_CFG 0x08
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#define XOFF_THRESHOLD_MASK 0x7ff
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#define XON_EN (1 << 11)
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#define TOTAL_XOFF_THRESHOLD_SHIFT 12
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#define TOTAL_XOFF_THRESHOLD_MASK 0x7ff
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#define TOTAL_XOFF_EN (1 << 23)
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#define TOTAL_XON_EN (1 << 24)
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#define PKTLEN_SHIFT 25
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#define PKTLEN_MASK 0x3f
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#define ACB_QUEUE_CFG(x) (ACB_QUEUE_0_CFG + ((x) * 0x4))
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/* Register set relative to 'CORE' */
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#define CORE_G_PCTL_PORT0 0x00000
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#define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
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#define CORE_IMP_CTL 0x00020
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#define RX_DIS (1 << 0)
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#define TX_DIS (1 << 1)
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#define RX_BCST_EN (1 << 2)
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#define RX_MCST_EN (1 << 3)
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#define RX_UCST_EN (1 << 4)
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#define CORE_SWMODE 0x0002c
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#define SW_FWDG_MODE (1 << 0)
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#define SW_FWDG_EN (1 << 1)
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#define RTRY_LMT_DIS (1 << 2)
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#define CORE_STS_OVERRIDE_IMP 0x00038
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#define GMII_SPEED_UP_2G (1 << 6)
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#define MII_SW_OR (1 << 7)
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/* Alternate layout for e.g: 7278 */
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#define CORE_STS_OVERRIDE_IMP2 0x39040
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#define CORE_NEW_CTRL 0x00084
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#define IP_MC (1 << 0)
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#define OUTRANGEERR_DISCARD (1 << 1)
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#define INRANGEERR_DISCARD (1 << 2)
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#define CABLE_DIAG_LEN (1 << 3)
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#define OVERRIDE_AUTO_PD_WAR (1 << 4)
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#define EN_AUTO_PD_WAR (1 << 5)
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#define UC_FWD_EN (1 << 6)
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#define MC_FWD_EN (1 << 7)
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#define CORE_SWITCH_CTRL 0x00088
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#define MII_DUMB_FWDG_EN (1 << 6)
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#define CORE_DIS_LEARN 0x000f0
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#define CORE_SFT_LRN_CTRL 0x000f8
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#define SW_LEARN_CNTL(x) (1 << (x))
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#define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
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#define CORE_STS_OVERRIDE_GMIIP2_PORT(x) (0x39000 + (x) * 8)
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#define LINK_STS (1 << 0)
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#define DUPLX_MODE (1 << 1)
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#define SPEED_SHIFT 2
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#define SPEED_MASK 0x3
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#define RXFLOW_CNTL (1 << 4)
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#define TXFLOW_CNTL (1 << 5)
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#define SW_OVERRIDE (1 << 6)
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#define CORE_WATCHDOG_CTRL 0x001e4
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#define SOFTWARE_RESET (1 << 7)
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#define EN_CHIP_RST (1 << 6)
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#define EN_SW_RESET (1 << 4)
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#define CORE_FAST_AGE_CTRL 0x00220
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#define EN_FAST_AGE_STATIC (1 << 0)
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#define EN_AGE_DYNAMIC (1 << 1)
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#define EN_AGE_PORT (1 << 2)
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#define EN_AGE_VLAN (1 << 3)
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#define EN_AGE_SPT (1 << 4)
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#define EN_AGE_MCAST (1 << 5)
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#define FAST_AGE_STR_DONE (1 << 7)
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#define CORE_FAST_AGE_PORT 0x00224
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#define AGE_PORT_MASK 0xf
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#define CORE_FAST_AGE_VID 0x00228
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#define AGE_VID_MASK 0x3fff
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#define CORE_LNKSTS 0x00400
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#define LNK_STS_MASK 0x1ff
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#define CORE_SPDSTS 0x00410
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#define SPDSTS_10 0
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#define SPDSTS_100 1
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#define SPDSTS_1000 2
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#define SPDSTS_SHIFT 2
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#define SPDSTS_MASK 0x3
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#define CORE_DUPSTS 0x00420
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#define CORE_DUPSTS_MASK 0x1ff
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#define CORE_PAUSESTS 0x00428
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#define PAUSESTS_TX_PAUSE_SHIFT 9
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#define CORE_GMNCFGCFG 0x0800
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#define RST_MIB_CNT (1 << 0)
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#define RXBPDU_EN (1 << 1)
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#define CORE_IMP0_PRT_ID 0x0804
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#define CORE_RST_MIB_CNT_EN 0x0950
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#define CORE_ARLA_VTBL_RWCTRL 0x1600
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#define ARLA_VTBL_CMD_WRITE 0
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#define ARLA_VTBL_CMD_READ 1
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#define ARLA_VTBL_CMD_CLEAR 2
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#define ARLA_VTBL_STDN (1 << 7)
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#define CORE_ARLA_VTBL_ADDR 0x1604
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#define VTBL_ADDR_INDEX_MASK 0xfff
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#define CORE_ARLA_VTBL_ENTRY 0x160c
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#define FWD_MAP_MASK 0x1ff
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#define UNTAG_MAP_MASK 0x1ff
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#define UNTAG_MAP_SHIFT 9
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#define MSTP_INDEX_MASK 0x7
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#define MSTP_INDEX_SHIFT 18
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#define FWD_MODE (1 << 21)
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#define CORE_MEM_PSM_VDD_CTRL 0x2380
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#define P_TXQ_PSM_VDD_SHIFT 2
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#define P_TXQ_PSM_VDD_MASK 0x3
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#define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
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((x) * P_TXQ_PSM_VDD_SHIFT))
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#define CORE_PORT_TC2_QOS_MAP_PORT(x) (0xc1c0 + ((x) * 0x10))
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#define PRT_TO_QID_MASK 0x3
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#define PRT_TO_QID_SHIFT 3
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#define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
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#define PORT_VLAN_CTRL_MASK 0x1ff
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#define CORE_TXQ_THD_PAUSE_QN_PORT_0 0x2c80
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#define TXQ_PAUSE_THD_MASK 0x7ff
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#define CORE_TXQ_THD_PAUSE_QN_PORT(x) (CORE_TXQ_THD_PAUSE_QN_PORT_0 + \
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(x) * 0x8)
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#define CORE_DEFAULT_1Q_TAG_P(x) (0xd040 + ((x) * 8))
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#define CFI_SHIFT 12
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#define PRI_SHIFT 13
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#define PRI_MASK 0x7
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#define CORE_JOIN_ALL_VLAN_EN 0xd140
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#define CORE_CFP_ACC 0x28000
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#define OP_STR_DONE (1 << 0)
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#define OP_SEL_SHIFT 1
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#define OP_SEL_READ (1 << OP_SEL_SHIFT)
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#define OP_SEL_WRITE (2 << OP_SEL_SHIFT)
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#define OP_SEL_SEARCH (4 << OP_SEL_SHIFT)
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#define OP_SEL_MASK (7 << OP_SEL_SHIFT)
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#define CFP_RAM_CLEAR (1 << 4)
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#define RAM_SEL_SHIFT 10
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#define TCAM_SEL (1 << RAM_SEL_SHIFT)
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#define ACT_POL_RAM (2 << RAM_SEL_SHIFT)
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#define RATE_METER_RAM (4 << RAM_SEL_SHIFT)
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#define GREEN_STAT_RAM (8 << RAM_SEL_SHIFT)
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#define YELLOW_STAT_RAM (16 << RAM_SEL_SHIFT)
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#define RED_STAT_RAM (24 << RAM_SEL_SHIFT)
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#define RAM_SEL_MASK (0x1f << RAM_SEL_SHIFT)
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#define TCAM_RESET (1 << 15)
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#define XCESS_ADDR_SHIFT 16
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#define XCESS_ADDR_MASK 0xff
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#define SEARCH_STS (1 << 27)
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#define RD_STS_SHIFT 28
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#define RD_STS_TCAM (1 << RD_STS_SHIFT)
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#define RD_STS_ACT_POL_RAM (2 << RD_STS_SHIFT)
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#define RD_STS_RATE_METER_RAM (4 << RD_STS_SHIFT)
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#define RD_STS_STAT_RAM (8 << RD_STS_SHIFT)
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#define CORE_CFP_RATE_METER_GLOBAL_CTL 0x28010
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#define CORE_CFP_DATA_PORT_0 0x28040
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#define CORE_CFP_DATA_PORT(x) (CORE_CFP_DATA_PORT_0 + \
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(x) * 0x10)
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/* UDF_DATA7 */
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#define L3_FRAMING_SHIFT 24
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#define L3_FRAMING_MASK (0x3 << L3_FRAMING_SHIFT)
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#define IPTOS_SHIFT 16
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#define IPTOS_MASK 0xff
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#define IPPROTO_SHIFT 8
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#define IPPROTO_MASK (0xff << IPPROTO_SHIFT)
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#define IP_FRAG_SHIFT 7
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#define IP_FRAG (1 << IP_FRAG_SHIFT)
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/* UDF_DATA0 */
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#define SLICE_VALID 3
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#define SLICE_NUM_SHIFT 2
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#define SLICE_NUM(x) ((x) << SLICE_NUM_SHIFT)
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#define SLICE_NUM_MASK 0x3
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#define CORE_CFP_MASK_PORT_0 0x280c0
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#define CORE_CFP_MASK_PORT(x) (CORE_CFP_MASK_PORT_0 + \
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(x) * 0x10)
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#define CORE_ACT_POL_DATA0 0x28140
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#define VLAN_BYP (1 << 0)
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#define EAP_BYP (1 << 1)
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#define STP_BYP (1 << 2)
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#define REASON_CODE_SHIFT 3
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#define REASON_CODE_MASK 0x3f
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#define LOOP_BK_EN (1 << 9)
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#define NEW_TC_SHIFT 10
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#define NEW_TC_MASK 0x7
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#define CHANGE_TC (1 << 13)
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#define DST_MAP_IB_SHIFT 14
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#define DST_MAP_IB_MASK 0x1ff
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#define CHANGE_FWRD_MAP_IB_SHIFT 24
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#define CHANGE_FWRD_MAP_IB_MASK 0x3
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#define CHANGE_FWRD_MAP_IB_NO_DEST (0 << CHANGE_FWRD_MAP_IB_SHIFT)
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#define CHANGE_FWRD_MAP_IB_REM_ARL (1 << CHANGE_FWRD_MAP_IB_SHIFT)
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#define CHANGE_FWRD_MAP_IB_REP_ARL (2 << CHANGE_FWRD_MAP_IB_SHIFT)
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#define CHANGE_FWRD_MAP_IB_ADD_DST (3 << CHANGE_FWRD_MAP_IB_SHIFT)
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#define NEW_DSCP_IB_SHIFT 26
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#define NEW_DSCP_IB_MASK 0x3f
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#define CORE_ACT_POL_DATA1 0x28150
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#define CHANGE_DSCP_IB (1 << 0)
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#define DST_MAP_OB_SHIFT 1
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#define DST_MAP_OB_MASK 0x3ff
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#define CHANGE_FWRD_MAP_OB_SHIT 11
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#define CHANGE_FWRD_MAP_OB_MASK 0x3
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#define NEW_DSCP_OB_SHIFT 13
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#define NEW_DSCP_OB_MASK 0x3f
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#define CHANGE_DSCP_OB (1 << 19)
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#define CHAIN_ID_SHIFT 20
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#define CHAIN_ID_MASK 0xff
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#define CHANGE_COLOR (1 << 28)
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#define NEW_COLOR_SHIFT 29
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#define NEW_COLOR_MASK 0x3
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#define NEW_COLOR_GREEN (0 << NEW_COLOR_SHIFT)
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#define NEW_COLOR_YELLOW (1 << NEW_COLOR_SHIFT)
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#define NEW_COLOR_RED (2 << NEW_COLOR_SHIFT)
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#define RED_DEFAULT (1 << 31)
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#define CORE_ACT_POL_DATA2 0x28160
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#define MAC_LIMIT_BYPASS (1 << 0)
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#define CHANGE_TC_O (1 << 1)
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#define NEW_TC_O_SHIFT 2
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#define NEW_TC_O_MASK 0x7
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#define SPCP_RMK_DISABLE (1 << 5)
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#define CPCP_RMK_DISABLE (1 << 6)
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#define DEI_RMK_DISABLE (1 << 7)
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#define CORE_RATE_METER0 0x28180
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#define COLOR_MODE (1 << 0)
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#define POLICER_ACTION (1 << 1)
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#define COUPLING_FLAG (1 << 2)
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#define POLICER_MODE_SHIFT 3
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#define POLICER_MODE_MASK 0x3
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#define POLICER_MODE_RFC2698 (0 << POLICER_MODE_SHIFT)
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#define POLICER_MODE_RFC4115 (1 << POLICER_MODE_SHIFT)
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#define POLICER_MODE_MEF (2 << POLICER_MODE_SHIFT)
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#define POLICER_MODE_DISABLE (3 << POLICER_MODE_SHIFT)
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#define CORE_RATE_METER1 0x28190
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#define EIR_TK_BKT_MASK 0x7fffff
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#define CORE_RATE_METER2 0x281a0
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#define EIR_BKT_SIZE_MASK 0xfffff
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#define CORE_RATE_METER3 0x281b0
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#define EIR_REF_CNT_MASK 0x7ffff
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#define CORE_RATE_METER4 0x281c0
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#define CIR_TK_BKT_MASK 0x7fffff
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#define CORE_RATE_METER5 0x281d0
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#define CIR_BKT_SIZE_MASK 0xfffff
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#define CORE_RATE_METER6 0x281e0
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#define CIR_REF_CNT_MASK 0x7ffff
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#define CORE_STAT_GREEN_CNTR 0x28200
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#define CORE_STAT_YELLOW_CNTR 0x28210
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#define CORE_STAT_RED_CNTR 0x28220
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#define CORE_CFP_CTL_REG 0x28400
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#define CFP_EN_MAP_MASK 0x1ff
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/* IPv4 slices, 3 of them */
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#define CORE_UDF_0_A_0_8_PORT_0 0x28440
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#define CFG_UDF_OFFSET_MASK 0x1f
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#define CFG_UDF_OFFSET_BASE_SHIFT 5
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#define CFG_UDF_SOF (0 << CFG_UDF_OFFSET_BASE_SHIFT)
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#define CFG_UDF_EOL2 (2 << CFG_UDF_OFFSET_BASE_SHIFT)
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#define CFG_UDF_EOL3 (3 << CFG_UDF_OFFSET_BASE_SHIFT)
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/* IPv6 slices */
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#define CORE_UDF_0_B_0_8_PORT_0 0x28500
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/* IPv6 chained slices */
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#define CORE_UDF_0_D_0_11_PORT_0 0x28680
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/* Number of slices for IPv4, IPv6 and non-IP */
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#define UDF_NUM_SLICES 4
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#define UDFS_PER_SLICE 9
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/* Spacing between different slices */
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#define UDF_SLICE_OFFSET 0x40
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#define CFP_NUM_RULES 256
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/* Number of egress queues per port */
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#define SF2_NUM_EGRESS_QUEUES 8
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#endif /* __BCM_SF2_REGS_H */
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