d2912cb15b
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
34 lines
730 B
C
34 lines
730 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* UFS Host driver for Synopsys Designware Core
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*
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* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
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*
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* Authors: Joao Pinto <jpinto@synopsys.com>
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*/
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#ifndef _UFSHCI_DWC_H
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#define _UFSHCI_DWC_H
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/* DWC HC UFSHCI specific Registers */
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enum dwc_specific_registers {
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DWC_UFS_REG_HCLKDIV = 0xFC,
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};
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/* Clock Divider Values: Hex equivalent of frequency in MHz */
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enum clk_div_values {
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DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
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DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
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DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
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};
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/* Selector Index */
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enum selector_index {
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SELIND_LN0_TX = 0x00,
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SELIND_LN1_TX = 0x01,
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SELIND_LN0_RX = 0x04,
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SELIND_LN1_RX = 0x05,
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};
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#endif /* End of Header */
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