73 lines
2.6 KiB
Plaintext
73 lines
2.6 KiB
Plaintext
* Power Management Controller
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Properties:
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- compatible: "fsl,<chip>-pmc".
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"fsl,mpc8349-pmc" should be listed for any chip whose PMC is
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compatible. "fsl,mpc8313-pmc" should also be listed for any chip
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whose PMC is compatible, and implies deep-sleep capability.
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"fsl,mpc8548-pmc" should be listed for any chip whose PMC is
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compatible. "fsl,mpc8536-pmc" should also be listed for any chip
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whose PMC is compatible, and implies deep-sleep capability and
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wake on user defined packet(wakeup on ARP).
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"fsl,p1022-pmc" should be listed for any chip whose PMC is
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compatible, and implies lossless Ethernet capability during sleep.
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"fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
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compatible; all statements below that apply to "fsl,mpc8548-pmc" also
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apply to "fsl,mpc8641d-pmc".
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Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
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bit assignments are indicated via the clock nodes. Device which has a
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controllable clock source should have a "fsl,pmc-handle" property pointing
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to the clock node.
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- reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
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is the PMC block, and the second resource is the Clock Configuration
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block.
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For devices compatible with "fsl,mpc8548-pmc", the first resource
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is a 32-byte block beginning with DEVDISR.
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- interrupts: For "fsl,mpc8349-pmc"-compatible devices, the first
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resource is the PMC block interrupt.
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- fsl,mpc8313-wakeup-timer: For "fsl,mpc8313-pmc"-compatible devices,
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this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
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a wakeup source from deep sleep.
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Clock nodes:
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The clock nodes are to describe the masks in PM controller registers for each
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soc clock.
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- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
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ORed into PMCDR before suspend if the device using this clock is the wake-up
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source and need to be running during low power mode; clear the mask if
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otherwise.
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- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
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bit specified by the mask in SCCR will be saved and cleared on suspend, and
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restored on resume.
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- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
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DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR
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or DEVDISR2 when the clock should be permenently disabled.
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Example:
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power@e0070 {
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compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
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reg = <0xe0070 0x20>;
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etsec1_clk: soc-clk@24 {
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fsl,pmcdr-mask = <0x00000080>;
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};
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etsec2_clk: soc-clk@25 {
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fsl,pmcdr-mask = <0x00000040>;
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};
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etsec3_clk: soc-clk@26 {
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fsl,pmcdr-mask = <0x00000020>;
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};
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};
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