17ee3e04dd
Display sw_in_discards, sw_in_filtered, and sw_out_filtered for chips supported by mv88e6123_61_65 and mv88e6352 drivers. The variables are provided in port registers, not the normal status registers. Mark by adding 0x100 to the register offset and add special handling code to mv88e6xxx_get_ethtool_stats. Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: David S. Miller <davem@davemloft.net>
789 lines
18 KiB
C
789 lines
18 KiB
C
/*
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* net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
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*
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* Copyright (c) 2014 Guenter Roeck
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*
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* Derived from mv88e6123_61_65.c
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* Copyright (c) 2008-2009 Marvell Semiconductor
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/delay.h>
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#include <linux/jiffies.h>
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#include <linux/list.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/platform_device.h>
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#include <linux/phy.h>
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#include <net/dsa.h>
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#include "mv88e6xxx.h"
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static int mv88e6352_wait(struct dsa_switch *ds, int reg, u16 mask)
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{
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unsigned long timeout = jiffies + HZ / 10;
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while (time_before(jiffies, timeout)) {
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int ret;
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ret = REG_READ(REG_GLOBAL2, reg);
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if (ret < 0)
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return ret;
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if (!(ret & mask))
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return 0;
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usleep_range(1000, 2000);
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}
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return -ETIMEDOUT;
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}
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static inline int mv88e6352_phy_wait(struct dsa_switch *ds)
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{
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return mv88e6352_wait(ds, 0x18, 0x8000);
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}
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static inline int mv88e6352_eeprom_load_wait(struct dsa_switch *ds)
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{
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return mv88e6352_wait(ds, 0x14, 0x0800);
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}
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static inline int mv88e6352_eeprom_busy_wait(struct dsa_switch *ds)
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{
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return mv88e6352_wait(ds, 0x14, 0x8000);
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}
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static int __mv88e6352_phy_read(struct dsa_switch *ds, int addr, int regnum)
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{
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int ret;
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REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);
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ret = mv88e6352_phy_wait(ds);
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if (ret < 0)
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return ret;
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return REG_READ(REG_GLOBAL2, 0x19);
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}
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static int __mv88e6352_phy_write(struct dsa_switch *ds, int addr, int regnum,
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u16 val)
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{
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REG_WRITE(REG_GLOBAL2, 0x19, val);
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REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);
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return mv88e6352_phy_wait(ds);
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}
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static char *mv88e6352_probe(struct device *host_dev, int sw_addr)
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{
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struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
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int ret;
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if (bus == NULL)
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return NULL;
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ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
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if (ret >= 0) {
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if ((ret & 0xfff0) == 0x1760)
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return "Marvell 88E6176";
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if (ret == 0x3521)
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return "Marvell 88E6352 (A0)";
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if (ret == 0x3522)
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return "Marvell 88E6352 (A1)";
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if ((ret & 0xfff0) == 0x3520)
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return "Marvell 88E6352";
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}
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return NULL;
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}
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static int mv88e6352_switch_reset(struct dsa_switch *ds)
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{
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unsigned long timeout;
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int ret;
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int i;
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/* Set all ports to the disabled state. */
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for (i = 0; i < 7; i++) {
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ret = REG_READ(REG_PORT(i), 0x04);
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REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
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}
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/* Wait for transmit queues to drain. */
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usleep_range(2000, 4000);
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/* Reset the switch. Keep PPU active (bit 14, undocumented).
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* The PPU needs to be active to support indirect phy register
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* accesses through global registers 0x18 and 0x19.
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*/
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REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
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/* Wait up to one second for reset to complete. */
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timeout = jiffies + 1 * HZ;
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while (time_before(jiffies, timeout)) {
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ret = REG_READ(REG_GLOBAL, 0x00);
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if ((ret & 0x8800) == 0x8800)
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break;
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usleep_range(1000, 2000);
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}
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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return 0;
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}
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static int mv88e6352_setup_global(struct dsa_switch *ds)
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{
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int ret;
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int i;
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/* Discard packets with excessive collisions,
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* mask all interrupt sources, enable PPU (bit 14, undocumented).
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*/
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REG_WRITE(REG_GLOBAL, 0x04, 0x6000);
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/* Set the default address aging time to 5 minutes, and
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* enable address learn messages to be sent to all message
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* ports.
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*/
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REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
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/* Configure the priority mapping registers. */
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ret = mv88e6xxx_config_prio(ds);
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if (ret < 0)
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return ret;
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/* Configure the upstream port, and configure the upstream
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* port as the port to which ingress and egress monitor frames
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* are to be sent.
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*/
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REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
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/* Disable remote management for now, and set the switch's
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* DSA device number.
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*/
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REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
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/* Send all frames with destination addresses matching
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* 01:80:c2:00:00:2x to the CPU port.
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*/
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REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
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/* Send all frames with destination addresses matching
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* 01:80:c2:00:00:0x to the CPU port.
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*/
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REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
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/* Disable the loopback filter, disable flow control
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* messages, disable flood broadcast override, disable
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* removing of provider tags, disable ATU age violation
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* interrupts, disable tag flow control, force flow
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* control priority to the highest, and send all special
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* multicast frames to the CPU at the highest priority.
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*/
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REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
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/* Program the DSA routing table. */
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for (i = 0; i < 32; i++) {
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int nexthop = 0x1f;
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if (i != ds->index && i < ds->dst->pd->nr_chips)
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nexthop = ds->pd->rtable[i] & 0x1f;
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REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
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}
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/* Clear all trunk masks. */
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for (i = 0; i < 8; i++)
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REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f);
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/* Clear all trunk mappings. */
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for (i = 0; i < 16; i++)
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REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
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/* Disable ingress rate limiting by resetting all ingress
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* rate limit registers to their initial state.
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*/
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for (i = 0; i < 7; i++)
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REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
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/* Initialise cross-chip port VLAN table to reset defaults. */
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REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
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/* Clear the priority override table. */
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for (i = 0; i < 16; i++)
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REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));
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/* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
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return 0;
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}
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static int mv88e6352_setup_port(struct dsa_switch *ds, int p)
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{
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int addr = REG_PORT(p);
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u16 val;
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/* MAC Forcing register: don't force link, speed, duplex
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* or flow control state to any particular values on physical
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* ports, but force the CPU port and all DSA ports to 1000 Mb/s
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* full duplex.
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*/
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if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
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REG_WRITE(addr, 0x01, 0x003e);
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else
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REG_WRITE(addr, 0x01, 0x0003);
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/* Do not limit the period of time that this port can be
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* paused for by the remote end or the period of time that
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* this port can pause the remote end.
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*/
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REG_WRITE(addr, 0x02, 0x0000);
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/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
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* disable Header mode, enable IGMP/MLD snooping, disable VLAN
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* tunneling, determine priority by looking at 802.1p and IP
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* priority fields (IP prio has precedence), and set STP state
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* to Forwarding.
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*
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* If this is the CPU link, use DSA or EDSA tagging depending
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* on which tagging mode was configured.
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*
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* If this is a link to another switch, use DSA tagging mode.
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*
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* If this is the upstream port for this switch, enable
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* forwarding of unknown unicasts and multicasts.
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*/
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val = 0x0433;
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if (dsa_is_cpu_port(ds, p)) {
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if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
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val |= 0x3300;
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else
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val |= 0x0100;
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}
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if (ds->dsa_port_mask & (1 << p))
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val |= 0x0100;
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if (p == dsa_upstream_port(ds))
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val |= 0x000c;
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REG_WRITE(addr, 0x04, val);
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/* Port Control 1: disable trunking. Also, if this is the
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* CPU port, enable learn messages to be sent to this port.
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*/
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REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
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/* Port based VLAN map: give each port its own address
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* database, allow the CPU port to talk to each of the 'real'
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* ports, and allow each of the 'real' ports to only talk to
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* the upstream port.
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*/
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val = (p & 0xf) << 12;
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if (dsa_is_cpu_port(ds, p))
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val |= ds->phys_port_mask;
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else
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val |= 1 << dsa_upstream_port(ds);
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REG_WRITE(addr, 0x06, val);
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/* Default VLAN ID and priority: don't set a default VLAN
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* ID, and set the default packet priority to zero.
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*/
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REG_WRITE(addr, 0x07, 0x0000);
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/* Port Control 2: don't force a good FCS, set the maximum
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* frame size to 10240 bytes, don't let the switch add or
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* strip 802.1q tags, don't discard tagged or untagged frames
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* on this port, do a destination address lookup on all
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* received packets as usual, disable ARP mirroring and don't
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* send a copy of all transmitted/received frames on this port
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* to the CPU.
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*/
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REG_WRITE(addr, 0x08, 0x2080);
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/* Egress rate control: disable egress rate control. */
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REG_WRITE(addr, 0x09, 0x0001);
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/* Egress rate control 2: disable egress rate control. */
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REG_WRITE(addr, 0x0a, 0x0000);
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/* Port Association Vector: when learning source addresses
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* of packets, add the address to the address database using
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* a port bitmap that has only the bit for this port set and
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* the other bits clear.
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*/
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REG_WRITE(addr, 0x0b, 1 << p);
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/* Port ATU control: disable limiting the number of address
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* database entries that this port is allowed to use.
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*/
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REG_WRITE(addr, 0x0c, 0x0000);
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/* Priority Override: disable DA, SA and VTU priority override. */
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REG_WRITE(addr, 0x0d, 0x0000);
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/* Port Ethertype: use the Ethertype DSA Ethertype value. */
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REG_WRITE(addr, 0x0f, ETH_P_EDSA);
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/* Tag Remap: use an identity 802.1p prio -> switch prio
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* mapping.
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*/
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REG_WRITE(addr, 0x18, 0x3210);
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/* Tag Remap 2: use an identity 802.1p prio -> switch prio
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* mapping.
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*/
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REG_WRITE(addr, 0x19, 0x7654);
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return 0;
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}
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#ifdef CONFIG_NET_DSA_HWMON
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static int mv88e6352_phy_page_read(struct dsa_switch *ds,
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int port, int page, int reg)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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mutex_lock(&ps->phy_mutex);
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ret = __mv88e6352_phy_write(ds, port, 0x16, page);
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if (ret < 0)
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goto error;
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ret = __mv88e6352_phy_read(ds, port, reg);
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error:
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__mv88e6352_phy_write(ds, port, 0x16, 0x0);
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mutex_unlock(&ps->phy_mutex);
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return ret;
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}
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static int mv88e6352_phy_page_write(struct dsa_switch *ds,
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int port, int page, int reg, int val)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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mutex_lock(&ps->phy_mutex);
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ret = __mv88e6352_phy_write(ds, port, 0x16, page);
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if (ret < 0)
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goto error;
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ret = __mv88e6352_phy_write(ds, port, reg, val);
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error:
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__mv88e6352_phy_write(ds, port, 0x16, 0x0);
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mutex_unlock(&ps->phy_mutex);
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return ret;
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}
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static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp)
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{
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int ret;
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*temp = 0;
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ret = mv88e6352_phy_page_read(ds, 0, 6, 27);
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if (ret < 0)
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return ret;
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*temp = (ret & 0xff) - 25;
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return 0;
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}
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static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp)
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{
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int ret;
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*temp = 0;
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ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
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if (ret < 0)
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return ret;
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*temp = (((ret >> 8) & 0x1f) * 5) - 25;
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return 0;
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}
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static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp)
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{
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int ret;
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ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
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if (ret < 0)
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return ret;
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temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
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return mv88e6352_phy_page_write(ds, 0, 6, 26,
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(ret & 0xe0ff) | (temp << 8));
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}
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static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
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{
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int ret;
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*alarm = false;
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ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
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if (ret < 0)
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return ret;
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*alarm = !!(ret & 0x40);
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return 0;
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}
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#endif /* CONFIG_NET_DSA_HWMON */
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static int mv88e6352_setup(struct dsa_switch *ds)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int ret;
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int i;
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mutex_init(&ps->smi_mutex);
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mutex_init(&ps->stats_mutex);
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mutex_init(&ps->phy_mutex);
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mutex_init(&ps->eeprom_mutex);
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ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
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ret = mv88e6352_switch_reset(ds);
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if (ret < 0)
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return ret;
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/* @@@ initialise vtu and atu */
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ret = mv88e6352_setup_global(ds);
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if (ret < 0)
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return ret;
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for (i = 0; i < 7; i++) {
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ret = mv88e6352_setup_port(ds, i);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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|
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static int mv88e6352_port_to_phy_addr(int port)
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{
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if (port >= 0 && port <= 4)
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return port;
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return -EINVAL;
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}
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|
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static int
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mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int addr = mv88e6352_port_to_phy_addr(port);
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int ret;
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if (addr < 0)
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return addr;
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mutex_lock(&ps->phy_mutex);
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ret = __mv88e6352_phy_read(ds, addr, regnum);
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mutex_unlock(&ps->phy_mutex);
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return ret;
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}
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|
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static int
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mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
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{
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struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
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int addr = mv88e6352_port_to_phy_addr(port);
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int ret;
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if (addr < 0)
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return addr;
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|
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mutex_lock(&ps->phy_mutex);
|
|
ret = __mv88e6352_phy_write(ds, addr, regnum, val);
|
|
mutex_unlock(&ps->phy_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = {
|
|
{ "in_good_octets", 8, 0x00, },
|
|
{ "in_bad_octets", 4, 0x02, },
|
|
{ "in_unicast", 4, 0x04, },
|
|
{ "in_broadcasts", 4, 0x06, },
|
|
{ "in_multicasts", 4, 0x07, },
|
|
{ "in_pause", 4, 0x16, },
|
|
{ "in_undersize", 4, 0x18, },
|
|
{ "in_fragments", 4, 0x19, },
|
|
{ "in_oversize", 4, 0x1a, },
|
|
{ "in_jabber", 4, 0x1b, },
|
|
{ "in_rx_error", 4, 0x1c, },
|
|
{ "in_fcs_error", 4, 0x1d, },
|
|
{ "out_octets", 8, 0x0e, },
|
|
{ "out_unicast", 4, 0x10, },
|
|
{ "out_broadcasts", 4, 0x13, },
|
|
{ "out_multicasts", 4, 0x12, },
|
|
{ "out_pause", 4, 0x15, },
|
|
{ "excessive", 4, 0x11, },
|
|
{ "collisions", 4, 0x1e, },
|
|
{ "deferred", 4, 0x05, },
|
|
{ "single", 4, 0x14, },
|
|
{ "multiple", 4, 0x17, },
|
|
{ "out_fcs_error", 4, 0x03, },
|
|
{ "late", 4, 0x1f, },
|
|
{ "hist_64bytes", 4, 0x08, },
|
|
{ "hist_65_127bytes", 4, 0x09, },
|
|
{ "hist_128_255bytes", 4, 0x0a, },
|
|
{ "hist_256_511bytes", 4, 0x0b, },
|
|
{ "hist_512_1023bytes", 4, 0x0c, },
|
|
{ "hist_1024_max_bytes", 4, 0x0d, },
|
|
{ "sw_in_discards", 4, 0x110, },
|
|
{ "sw_in_filtered", 2, 0x112, },
|
|
{ "sw_out_filtered", 2, 0x113, },
|
|
};
|
|
|
|
static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int ret;
|
|
|
|
mutex_lock(&ps->eeprom_mutex);
|
|
|
|
ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14,
|
|
0xc000 | (addr & 0xff));
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
ret = mv88e6352_eeprom_busy_wait(ds);
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x15);
|
|
error:
|
|
mutex_unlock(&ps->eeprom_mutex);
|
|
return ret;
|
|
}
|
|
|
|
static int mv88e6352_get_eeprom(struct dsa_switch *ds,
|
|
struct ethtool_eeprom *eeprom, u8 *data)
|
|
{
|
|
int offset;
|
|
int len;
|
|
int ret;
|
|
|
|
offset = eeprom->offset;
|
|
len = eeprom->len;
|
|
eeprom->len = 0;
|
|
|
|
eeprom->magic = 0xc3ec4951;
|
|
|
|
ret = mv88e6352_eeprom_load_wait(ds);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (offset & 1) {
|
|
int word;
|
|
|
|
word = mv88e6352_read_eeprom_word(ds, offset >> 1);
|
|
if (word < 0)
|
|
return word;
|
|
|
|
*data++ = (word >> 8) & 0xff;
|
|
|
|
offset++;
|
|
len--;
|
|
eeprom->len++;
|
|
}
|
|
|
|
while (len >= 2) {
|
|
int word;
|
|
|
|
word = mv88e6352_read_eeprom_word(ds, offset >> 1);
|
|
if (word < 0)
|
|
return word;
|
|
|
|
*data++ = word & 0xff;
|
|
*data++ = (word >> 8) & 0xff;
|
|
|
|
offset += 2;
|
|
len -= 2;
|
|
eeprom->len += 2;
|
|
}
|
|
|
|
if (len) {
|
|
int word;
|
|
|
|
word = mv88e6352_read_eeprom_word(ds, offset >> 1);
|
|
if (word < 0)
|
|
return word;
|
|
|
|
*data++ = word & 0xff;
|
|
|
|
offset++;
|
|
len--;
|
|
eeprom->len++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
|
|
{
|
|
int ret;
|
|
|
|
ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x14);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (!(ret & 0x0400))
|
|
return -EROFS;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
|
|
u16 data)
|
|
{
|
|
struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
|
|
int ret;
|
|
|
|
mutex_lock(&ps->eeprom_mutex);
|
|
|
|
ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x15, data);
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14,
|
|
0xb000 | (addr & 0xff));
|
|
if (ret < 0)
|
|
goto error;
|
|
|
|
ret = mv88e6352_eeprom_busy_wait(ds);
|
|
error:
|
|
mutex_unlock(&ps->eeprom_mutex);
|
|
return ret;
|
|
}
|
|
|
|
static int mv88e6352_set_eeprom(struct dsa_switch *ds,
|
|
struct ethtool_eeprom *eeprom, u8 *data)
|
|
{
|
|
int offset;
|
|
int ret;
|
|
int len;
|
|
|
|
if (eeprom->magic != 0xc3ec4951)
|
|
return -EINVAL;
|
|
|
|
ret = mv88e6352_eeprom_is_readonly(ds);
|
|
if (ret)
|
|
return ret;
|
|
|
|
offset = eeprom->offset;
|
|
len = eeprom->len;
|
|
eeprom->len = 0;
|
|
|
|
ret = mv88e6352_eeprom_load_wait(ds);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
if (offset & 1) {
|
|
int word;
|
|
|
|
word = mv88e6352_read_eeprom_word(ds, offset >> 1);
|
|
if (word < 0)
|
|
return word;
|
|
|
|
word = (*data++ << 8) | (word & 0xff);
|
|
|
|
ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
offset++;
|
|
len--;
|
|
eeprom->len++;
|
|
}
|
|
|
|
while (len >= 2) {
|
|
int word;
|
|
|
|
word = *data++;
|
|
word |= *data++ << 8;
|
|
|
|
ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
offset += 2;
|
|
len -= 2;
|
|
eeprom->len += 2;
|
|
}
|
|
|
|
if (len) {
|
|
int word;
|
|
|
|
word = mv88e6352_read_eeprom_word(ds, offset >> 1);
|
|
if (word < 0)
|
|
return word;
|
|
|
|
word = (word & 0xff00) | *data++;
|
|
|
|
ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
offset++;
|
|
len--;
|
|
eeprom->len++;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
|
|
{
|
|
mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats),
|
|
mv88e6352_hw_stats, port, data);
|
|
}
|
|
|
|
static void
|
|
mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
|
|
{
|
|
mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats),
|
|
mv88e6352_hw_stats, port, data);
|
|
}
|
|
|
|
static int mv88e6352_get_sset_count(struct dsa_switch *ds)
|
|
{
|
|
return ARRAY_SIZE(mv88e6352_hw_stats);
|
|
}
|
|
|
|
struct dsa_switch_driver mv88e6352_switch_driver = {
|
|
.tag_protocol = DSA_TAG_PROTO_EDSA,
|
|
.priv_size = sizeof(struct mv88e6xxx_priv_state),
|
|
.probe = mv88e6352_probe,
|
|
.setup = mv88e6352_setup,
|
|
.set_addr = mv88e6xxx_set_addr_indirect,
|
|
.phy_read = mv88e6352_phy_read,
|
|
.phy_write = mv88e6352_phy_write,
|
|
.poll_link = mv88e6xxx_poll_link,
|
|
.get_strings = mv88e6352_get_strings,
|
|
.get_ethtool_stats = mv88e6352_get_ethtool_stats,
|
|
.get_sset_count = mv88e6352_get_sset_count,
|
|
#ifdef CONFIG_NET_DSA_HWMON
|
|
.get_temp = mv88e6352_get_temp,
|
|
.get_temp_limit = mv88e6352_get_temp_limit,
|
|
.set_temp_limit = mv88e6352_set_temp_limit,
|
|
.get_temp_alarm = mv88e6352_get_temp_alarm,
|
|
#endif
|
|
.get_eeprom = mv88e6352_get_eeprom,
|
|
.set_eeprom = mv88e6352_set_eeprom,
|
|
.get_regs_len = mv88e6xxx_get_regs_len,
|
|
.get_regs = mv88e6xxx_get_regs,
|
|
};
|
|
|
|
MODULE_ALIAS("platform:mv88e6352");
|