![Valentine Barshak](/assets/img/avatar_default.png)
Bootwrapper code for AMCC PPC440EPx Sequoia. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
301 lines
7 KiB
C
301 lines
7 KiB
C
/*
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* Copyright 2007 David Gibson, IBM Corporation.
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*
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* Based on earlier code:
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003, 2004 Zultys Technologies
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <stddef.h>
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#include "types.h"
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#include "string.h"
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#include "stdio.h"
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#include "ops.h"
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#include "reg.h"
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#include "dcr.h"
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/* Read the 4xx SDRAM controller to get size of system memory. */
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void ibm4xx_fixup_memsize(void)
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{
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int i;
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unsigned long memsize, bank_config;
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memsize = 0;
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for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
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mtdcr(DCRN_SDRAM0_CFGADDR, sdram_bxcr[i]);
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bank_config = mfdcr(DCRN_SDRAM0_CFGDATA);
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if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
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memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
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}
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dt_fixup_memory(0, memsize);
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}
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/* 4xx DDR1/2 Denali memory controller support */
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/* DDR0 registers */
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#define DDR0_02 2
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#define DDR0_08 8
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#define DDR0_10 10
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#define DDR0_14 14
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#define DDR0_42 42
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#define DDR0_43 43
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/* DDR0_02 */
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#define DDR_START 0x1
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#define DDR_START_SHIFT 0
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#define DDR_MAX_CS_REG 0x3
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#define DDR_MAX_CS_REG_SHIFT 24
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#define DDR_MAX_COL_REG 0xf
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#define DDR_MAX_COL_REG_SHIFT 16
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#define DDR_MAX_ROW_REG 0xf
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#define DDR_MAX_ROW_REG_SHIFT 8
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/* DDR0_08 */
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#define DDR_DDR2_MODE 0x1
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#define DDR_DDR2_MODE_SHIFT 0
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/* DDR0_10 */
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#define DDR_CS_MAP 0x3
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#define DDR_CS_MAP_SHIFT 8
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/* DDR0_14 */
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#define DDR_REDUC 0x1
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#define DDR_REDUC_SHIFT 16
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/* DDR0_42 */
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#define DDR_APIN 0x7
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#define DDR_APIN_SHIFT 24
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/* DDR0_43 */
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#define DDR_COL_SZ 0x7
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#define DDR_COL_SZ_SHIFT 8
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#define DDR_BANK8 0x1
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#define DDR_BANK8_SHIFT 0
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#define DDR_GET_VAL(val, mask, shift) (((val) >> (shift)) & (mask))
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static inline u32 mfdcr_sdram0(u32 reg)
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{
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mtdcr(DCRN_SDRAM0_CFGADDR, reg);
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return mfdcr(DCRN_SDRAM0_CFGDATA);
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}
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void ibm4xx_denali_fixup_memsize(void)
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{
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u32 val, max_cs, max_col, max_row;
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u32 cs, col, row, bank, dpath;
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unsigned long memsize;
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val = mfdcr_sdram0(DDR0_02);
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if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
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fatal("DDR controller is not initialized\n");
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/* get maximum cs col and row values */
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max_cs = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
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max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
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max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
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/* get CS value */
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val = mfdcr_sdram0(DDR0_10);
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val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
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cs = 0;
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while (val) {
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if (val && 0x1)
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cs++;
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val = val >> 1;
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}
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if (!cs)
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fatal("No memory installed\n");
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if (cs > max_cs)
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fatal("DDR wrong CS configuration\n");
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/* get data path bytes */
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val = mfdcr_sdram0(DDR0_14);
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if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
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dpath = 8; /* 64 bits */
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else
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dpath = 4; /* 32 bits */
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/* get adress pins (rows) */
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val = mfdcr_sdram0(DDR0_42);
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row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
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if (row > max_row)
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fatal("DDR wrong APIN configuration\n");
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row = max_row - row;
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/* get collomn size and banks */
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val = mfdcr_sdram0(DDR0_43);
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col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
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if (col > max_col)
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fatal("DDR wrong COL configuration\n");
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col = max_col - col;
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if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
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bank = 8; /* 8 banks */
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else
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bank = 4; /* 4 banks */
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memsize = cs * (1 << (col+row)) * bank * dpath;
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dt_fixup_memory(0, memsize);
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}
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#define SPRN_DBCR0_40X 0x3F2
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#define SPRN_DBCR0_44X 0x134
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#define DBCR0_RST_SYSTEM 0x30000000
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void ibm44x_dbcr_reset(void)
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{
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unsigned long tmp;
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asm volatile (
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"mfspr %0,%1\n"
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"oris %0,%0,%2@h\n"
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"mtspr %1,%0"
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: "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
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);
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}
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void ibm40x_dbcr_reset(void)
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{
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unsigned long tmp;
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asm volatile (
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"mfspr %0,%1\n"
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"oris %0,%0,%2@h\n"
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"mtspr %1,%0"
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: "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
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);
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}
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#define EMAC_RESET 0x20000000
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void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
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{
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/* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't do this for us */
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if (emac0)
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*emac0 = EMAC_RESET;
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if (emac1)
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*emac1 = EMAC_RESET;
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mtdcr(DCRN_MAL0_CFG, MAL_RESET);
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}
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/* Read 4xx EBC bus bridge registers to get mappings of the peripheral
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* banks into the OPB address space */
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void ibm4xx_fixup_ebc_ranges(const char *ebc)
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{
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void *devp;
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u32 bxcr;
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u32 ranges[EBC_NUM_BANKS*4];
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u32 *p = ranges;
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int i;
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for (i = 0; i < EBC_NUM_BANKS; i++) {
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mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
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bxcr = mfdcr(DCRN_EBC0_CFGDATA);
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if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
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*p++ = i;
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*p++ = 0;
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*p++ = bxcr & EBC_BXCR_BAS;
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*p++ = EBC_BXCR_BANK_SIZE(bxcr);
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}
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}
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devp = finddevice(ebc);
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if (! devp)
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fatal("Couldn't locate EBC node %s\n\r", ebc);
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setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
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}
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#define SPRN_CCR1 0x378
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void ibm440ep_fixup_clocks(unsigned int sysclk, unsigned int ser_clk)
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{
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u32 cpu, plb, opb, ebc, tb, uart0, m, vco;
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u32 reg;
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u32 fwdva, fwdvb, fbdv, lfbdv, opbdv0, perdv0, spcid0, prbdv0, tmp;
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mtdcr(DCRN_CPR0_ADDR, CPR0_PLLD0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x000F0000) >> 16;
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fwdva = tmp ? tmp : 16;
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tmp = (reg & 0x00000700) >> 8;
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fwdvb = tmp ? tmp : 8;
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tmp = (reg & 0x1F000000) >> 24;
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fbdv = tmp ? tmp : 32;
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lfbdv = (reg & 0x0000007F);
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mtdcr(DCRN_CPR0_ADDR, CPR0_OPBD0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x03000000) >> 24;
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opbdv0 = tmp ? tmp : 4;
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mtdcr(DCRN_CPR0_ADDR, CPR0_PERD0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x07000000) >> 24;
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perdv0 = tmp ? tmp : 8;
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mtdcr(DCRN_CPR0_ADDR, CPR0_PRIMBD0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x07000000) >> 24;
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prbdv0 = tmp ? tmp : 8;
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mtdcr(DCRN_CPR0_ADDR, CPR0_SCPID);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x03000000) >> 24;
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spcid0 = tmp ? tmp : 4;
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/* Calculate M */
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mtdcr(DCRN_CPR0_ADDR, CPR0_PLLC0);
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reg = mfdcr(DCRN_CPR0_DATA);
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tmp = (reg & 0x03000000) >> 24;
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if (tmp == 0) { /* PLL output */
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tmp = (reg & 0x20000000) >> 29;
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if (!tmp) /* PLLOUTA */
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m = fbdv * lfbdv * fwdva;
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else
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m = fbdv * lfbdv * fwdvb;
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}
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else if (tmp == 1) /* CPU output */
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m = fbdv * fwdva;
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else
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m = perdv0 * opbdv0 * fwdvb;
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vco = (m * sysclk) + (m >> 1);
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cpu = vco / fwdva;
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plb = vco / fwdvb / prbdv0;
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opb = plb / opbdv0;
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ebc = plb / perdv0;
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/* FIXME */
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uart0 = ser_clk;
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/* Figure out timebase. Either CPU or default TmrClk */
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asm volatile (
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"mfspr %0,%1\n"
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:
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"=&r"(reg) : "i"(SPRN_CCR1));
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if (reg & 0x0080)
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tb = 25000000; /* TmrClk is 25MHz */
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else
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tb = cpu;
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dt_fixup_cpu_clocks(cpu, tb, 0);
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dt_fixup_clock("/plb", plb);
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dt_fixup_clock("/plb/opb", opb);
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dt_fixup_clock("/plb/opb/ebc", ebc);
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dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
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dt_fixup_clock("/plb/opb/serial@ef600400", uart0);
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dt_fixup_clock("/plb/opb/serial@ef600500", uart0);
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dt_fixup_clock("/plb/opb/serial@ef600600", uart0);
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}
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