88253e8459
This zeroes out the number of cache aliases in the cache info descriptors when hardware alias avoidance is enabled. This cuts down on the amount of flushing taken care of by common code, and also permits coherency control to be disabled for the single CPU and 4k page size case. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
45 lines
1,020 B
C
45 lines
1,020 B
C
/*
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* arch/sh/mm/cache-shx3.c - SH-X3 optimized cache ops
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*
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* Copyright (C) 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <asm/cache.h>
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#define CCR_CACHE_SNM 0x40000 /* Hardware-assisted synonym avoidance */
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#define CCR_CACHE_IBE 0x1000000 /* ICBI broadcast */
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void __init shx3_cache_init(void)
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{
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unsigned int ccr;
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ccr = __raw_readl(CCR);
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/*
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* If we've got cache aliases, resolve them in hardware.
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*/
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if (boot_cpu_data.dcache.n_aliases || boot_cpu_data.icache.n_aliases) {
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ccr |= CCR_CACHE_SNM;
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boot_cpu_data.icache.n_aliases = 0;
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boot_cpu_data.dcache.n_aliases = 0;
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pr_info("Enabling hardware synonym avoidance\n");
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}
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#ifdef CONFIG_SMP
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/*
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* Broadcast I-cache block invalidations by default.
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*/
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ccr |= CCR_CACHE_IBE;
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#endif
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writel_uncached(ccr, CCR);
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}
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