65 lines
1.4 KiB
C
65 lines
1.4 KiB
C
#ifndef __ASM_ARM_CPUTYPE_H
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#define __ASM_ARM_CPUTYPE_H
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#include <linux/stringify.h>
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#define CPUID_ID 0
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#define CPUID_CACHETYPE 1
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#define CPUID_TCM 2
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#define CPUID_TLBTYPE 3
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#ifdef CONFIG_CPU_CP15
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#define read_cpuid(reg) \
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({ \
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unsigned int __val; \
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asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
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: "=r" (__val) \
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: \
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: "cc"); \
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__val; \
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})
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#else
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extern unsigned int processor_id;
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#define read_cpuid(reg) (processor_id)
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#endif
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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* rather than directly reading processor_id or read_cpuid() directly.
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*/
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static inline unsigned int __attribute_const__ read_cpuid_id(void)
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{
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return read_cpuid(CPUID_ID);
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}
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static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
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{
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return read_cpuid(CPUID_CACHETYPE);
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}
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/*
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* Intel's XScale3 core supports some v6 features (supersections, L2)
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* but advertises itself as v5 as it does not support the v6 ISA. For
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* this reason, we need a way to explicitly test for this type of CPU.
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*/
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#ifndef CONFIG_CPU_XSC3
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#define cpu_is_xsc3() 0
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#else
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static inline int cpu_is_xsc3(void)
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{
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if ((read_cpuid_id() & 0xffffe000) == 0x69056000)
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return 1;
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return 0;
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}
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#endif
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#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
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#define cpu_is_xscale() 0
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#else
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#define cpu_is_xscale() 1
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#endif
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#endif
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