0c3091ad45
PLL clocks are basis clock for other clock. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
270 lines
6.7 KiB
C
270 lines
6.7 KiB
C
/*
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* r8a73a4 clock framework support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x270
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#define MPCKCR 0xe6150080
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR5 0xe6150144
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#define CKSCR 0xE61500C0
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#define PLLECR 0xE61500D0
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#define PLL1CR 0xE6150028
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#define PLL2CR 0xE615002C
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#define PLL2SCR 0xE61501F4
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#define PLL2HCR 0xE61501E4
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#define CPG_MAP(o) ((o - CPG_BASE) + cpg_mapping.base)
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static struct clk_mapping cpg_mapping = {
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.phys = CPG_BASE,
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.len = CPG_LEN,
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};
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static struct clk extalr_clk = {
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.rate = 32768,
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.mapping = &cpg_mapping,
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};
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static struct clk extal1_clk = {
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.rate = 26000000,
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.mapping = &cpg_mapping,
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};
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static struct clk extal2_clk = {
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.rate = 48000000,
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.mapping = &cpg_mapping,
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};
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static struct sh_clk_ops followparent_clk_ops = {
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.recalc = followparent_recalc,
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};
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static struct clk main_clk = {
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/* .parent will be set r8a73a4_clock_init */
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.ops = &followparent_clk_ops,
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};
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SH_CLK_RATIO(div2, 1, 2);
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SH_CLK_RATIO(div4, 1, 4);
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SH_FIXED_RATIO_CLK(main_div2_clk, main_clk, div2);
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SH_FIXED_RATIO_CLK(extal1_div2_clk, extal1_clk, div2);
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SH_FIXED_RATIO_CLK(extal2_div2_clk, extal2_clk, div2);
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SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_clk, div4);
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/*
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* PLL clocks
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*/
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static struct clk *pll_parent_main[] = {
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[0] = &main_clk,
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[1] = &main_div2_clk
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};
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static struct clk *pll_parent_main_extal[8] = {
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[0] = &main_div2_clk,
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[1] = &extal2_div2_clk,
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[3] = &extal2_div4_clk,
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[4] = &main_clk,
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[5] = &extal2_clk,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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unsigned long mult = 1;
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if (ioread32(CPG_MAP(PLLECR)) & (1 << clk->enable_bit))
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mult = (((ioread32(clk->mapped_reg) >> 24) & 0x7f) + 1);
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return clk->parent->rate * mult;
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}
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static int pll_set_parent(struct clk *clk, struct clk *parent)
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{
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u32 val;
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int i, ret;
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if (!clk->parent_table || !clk->parent_num)
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return -EINVAL;
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/* Search the parent */
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for (i = 0; i < clk->parent_num; i++)
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if (clk->parent_table[i] == parent)
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break;
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if (i == clk->parent_num)
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return -ENODEV;
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ret = clk_reparent(clk, parent);
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if (ret < 0)
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return ret;
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val = ioread32(clk->mapped_reg) &
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~(((1 << clk->src_width) - 1) << clk->src_shift);
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iowrite32(val | i << clk->src_shift, clk->mapped_reg);
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return 0;
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}
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static struct sh_clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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.set_parent = pll_set_parent,
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};
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#define PLL_CLOCK(name, p, pt, w, s, reg, e) \
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static struct clk name = { \
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.ops = &pll_clk_ops, \
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.flags = CLK_ENABLE_ON_INIT, \
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.parent = p, \
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.parent_table = pt, \
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.parent_num = ARRAY_SIZE(pt), \
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.src_width = w, \
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.src_shift = s, \
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.enable_reg = (void __iomem *)reg, \
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.enable_bit = e, \
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.mapping = &cpg_mapping, \
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}
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PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
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PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
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PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
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PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
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SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
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static struct clk *main_clks[] = {
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&extalr_clk,
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&extal1_clk,
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&extal1_div2_clk,
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&extal2_clk,
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&extal2_div2_clk,
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&extal2_div4_clk,
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&main_clk,
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&main_div2_clk,
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&pll1_clk,
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&pll1_div2_clk,
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&pll2_clk,
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&pll2s_clk,
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&pll2h_clk,
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};
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enum {
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MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
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MSTP522,
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MSTP_NR
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP204] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP206] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
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[MSTP207] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
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[MSTP216] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
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[MSTP217] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR2, 17, 0), /* SCIFB3 */
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[MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
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};
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static struct clk_lookup lookups[] = {
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/* main clock */
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CLKDEV_CON_ID("extal1", &extal1_clk),
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CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
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CLKDEV_CON_ID("extal2", &extal2_clk),
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CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
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CLKDEV_CON_ID("extal2_div4", &extal2_div4_clk),
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/* pll clock */
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CLKDEV_CON_ID("pll1", &pll1_clk),
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CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
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CLKDEV_CON_ID("pll2", &pll2_clk),
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CLKDEV_CON_ID("pll2s", &pll2s_clk),
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CLKDEV_CON_ID("pll2h", &pll2h_clk),
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/* MSTP */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
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CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
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/* for DT */
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CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
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};
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void __init r8a73a4_clock_init(void)
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{
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void __iomem *cpg_base, *reg;
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int k, ret = 0;
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u32 ckscr;
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/* fix MPCLK to EXTAL2 for now.
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* this is needed until more detailed clock topology is supported
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*/
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cpg_base = ioremap_nocache(CPG_BASE, CPG_LEN);
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BUG_ON(!cpg_base);
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reg = cpg_base + (MPCKCR - CPG_BASE);
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iowrite32(ioread32(reg) | 1 << 7 | 0x0c, reg); /* set CKSEL */
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iounmap(cpg_base);
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reg = ioremap_nocache(CKSCR, PAGE_SIZE);
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BUG_ON(!reg);
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ckscr = ioread32(reg);
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iounmap(reg);
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switch ((ckscr >> 28) & 0x3) {
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case 0:
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main_clk.parent = &extal1_clk;
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break;
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case 1:
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main_clk.parent = &extal1_div2_clk;
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break;
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case 2:
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main_clk.parent = &extal2_clk;
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break;
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case 3:
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main_clk.parent = &extal2_div2_clk;
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break;
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}
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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if (!ret)
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shmobile_clk_init();
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else
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panic("failed to setup r8a73a4 clocks\n");
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}
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