![Andy Shevchenko](/assets/img/avatar_default.png)
There are more that one SPI controller on the Intel MID boards. This patch describes the status and IDs of them. From now on we also have to care about bus number that must be unique per host. According to the specification the SPI1 has 5 bits for chip selects and SPI2 only 2 bits. The patch makes it depend to PCI ID. The first controller (SPI1) is DMA capable, meanwhile SPI2 can share same channels (via software switch) such functionality is not in the scope of this patch. Thus, attempt to init DMA for SPI2 will always fail for now. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
327 lines
9.1 KiB
C
327 lines
9.1 KiB
C
/*
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* Intel MID PCI support
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* Copyright (c) 2008 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Moorestown has an interesting PCI implementation:
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* - configuration space is memory mapped (as defined by MCFG)
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* - Lincroft devices also have a real, type 1 configuration space
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* - Early Lincroft silicon has a type 1 access bug that will cause
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* a hang if non-existent devices are accessed
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* - some devices have the "fixed BAR" capability, which means
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* they can't be relocated or modified; check for that during
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* BAR sizing
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*
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* So, we use the MCFG space for all reads and writes, but also send
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* Lincroft writes to type 1 space. But only read/write if the device
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* actually exists, otherwise return all 1s for reads and bit bucket
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* the writes.
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*/
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#include <linux/sched.h>
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#include <linux/pci.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/dmi.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <asm/segment.h>
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#include <asm/pci_x86.h>
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#include <asm/hw_irq.h>
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#include <asm/io_apic.h>
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#include <asm/intel-mid.h>
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#define PCIE_CAP_OFFSET 0x100
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/* Fixed BAR fields */
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#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
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#define PCI_FIXED_BAR_0_SIZE 0x04
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#define PCI_FIXED_BAR_1_SIZE 0x08
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#define PCI_FIXED_BAR_2_SIZE 0x0c
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#define PCI_FIXED_BAR_3_SIZE 0x10
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#define PCI_FIXED_BAR_4_SIZE 0x14
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#define PCI_FIXED_BAR_5_SIZE 0x1c
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static int pci_soc_mode;
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/**
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* fixed_bar_cap - return the offset of the fixed BAR cap if found
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* @bus: PCI bus
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* @devfn: device in question
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*
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* Look for the fixed BAR cap on @bus and @devfn, returning its offset
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* if found or 0 otherwise.
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*/
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static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
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{
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int pos;
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u32 pcie_cap = 0, cap_data;
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pos = PCIE_CAP_OFFSET;
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if (!raw_pci_ext_ops)
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return 0;
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while (pos) {
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if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
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devfn, pos, 4, &pcie_cap))
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return 0;
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if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
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PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
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break;
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if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
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raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
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devfn, pos + 4, 4, &cap_data);
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if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
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return pos;
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}
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pos = PCI_EXT_CAP_NEXT(pcie_cap);
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}
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return 0;
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}
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static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
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int reg, int len, u32 val, int offset)
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{
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u32 size;
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unsigned int domain, busnum;
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int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
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domain = pci_domain_nr(bus);
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busnum = bus->number;
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if (val == ~0 && len == 4) {
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unsigned long decode;
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raw_pci_ext_ops->read(domain, busnum, devfn,
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offset + 8 + (bar * 4), 4, &size);
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/* Turn the size into a decode pattern for the sizing code */
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if (size) {
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decode = size - 1;
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decode |= decode >> 1;
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decode |= decode >> 2;
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decode |= decode >> 4;
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decode |= decode >> 8;
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decode |= decode >> 16;
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decode++;
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decode = ~(decode - 1);
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} else {
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decode = 0;
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}
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/*
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* If val is all ones, the core code is trying to size the reg,
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* so update the mmconfig space with the real size.
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*
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* Note: this assumes the fixed size we got is a power of two.
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*/
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return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
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decode);
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}
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/* This is some other kind of BAR write, so just do it. */
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return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
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}
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/**
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* type1_access_ok - check whether to use type 1
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* @bus: bus number
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* @devfn: device & function in question
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*
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* If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
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* all, the we can go ahead with any reads & writes. If it's on a Lincroft,
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* but doesn't exist, avoid the access altogether to keep the chip from
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* hanging.
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*/
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static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
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{
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/*
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* This is a workaround for A0 LNC bug where PCI status register does
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* not have new CAP bit set. can not be written by SW either.
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*
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* PCI header type in real LNC indicates a single function device, this
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* will prevent probing other devices under the same function in PCI
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* shim. Therefore, use the header type in shim instead.
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*/
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if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
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return false;
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if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
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|| devfn == PCI_DEVFN(0, 0)
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|| devfn == PCI_DEVFN(3, 0)))
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return true;
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return false; /* Langwell on others */
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}
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static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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if (type1_access_ok(bus->number, devfn, where))
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return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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}
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static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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int offset;
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/*
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* On MRST, there is no PCI ROM BAR, this will cause a subsequent read
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* to ROM BAR return 0 then being ignored.
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*/
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if (where == PCI_ROM_ADDRESS)
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return 0;
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/*
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* Devices with fixed BARs need special handling:
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* - BAR sizing code will save, write ~0, read size, restore
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* - so writes to fixed BARs need special handling
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* - other writes to fixed BAR devices should go through mmconfig
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*/
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offset = fixed_bar_cap(bus, devfn);
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if (offset &&
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(where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
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return pci_device_update_fixed(bus, devfn, where, size, value,
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offset);
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}
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/*
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* On Moorestown update both real & mmconfig space
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* Note: early Lincroft silicon can't handle type 1 accesses to
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* non-existent devices, so just eat the write in that case.
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*/
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if (type1_access_ok(bus->number, devfn, where))
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return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
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devfn, where, size, value);
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return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
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where, size, value);
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}
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static int intel_mid_pci_irq_enable(struct pci_dev *dev)
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{
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int polarity;
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if (dev->irq_managed && dev->irq > 0)
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return 0;
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if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
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polarity = 0; /* active high */
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else
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polarity = 1; /* active low */
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/*
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* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
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* IOAPIC RTE entries, so we just enable RTE for the device.
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*/
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if (mp_set_gsi_attr(dev->irq, 1, polarity, dev_to_node(&dev->dev)))
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return -EBUSY;
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if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0)
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return -EBUSY;
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dev->irq_managed = 1;
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return 0;
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}
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static void intel_mid_pci_irq_disable(struct pci_dev *dev)
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{
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if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
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dev->irq > 0) {
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mp_unmap_irq(dev->irq);
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dev->irq_managed = 0;
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}
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}
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struct pci_ops intel_mid_pci_ops = {
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.read = pci_read,
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.write = pci_write,
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};
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/**
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* intel_mid_pci_init - installs intel_mid_pci_ops
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*
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* Moorestown has an interesting PCI implementation (see above).
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* Called when the early platform detection installs it.
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*/
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int __init intel_mid_pci_init(void)
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{
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pr_info("Intel MID platform detected, using MID PCI ops\n");
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pci_mmcfg_late_init();
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pcibios_enable_irq = intel_mid_pci_irq_enable;
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pcibios_disable_irq = intel_mid_pci_irq_disable;
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pci_root_ops = intel_mid_pci_ops;
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pci_soc_mode = 1;
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/* Continue with standard init */
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return 1;
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}
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/*
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* Langwell devices are not true PCI devices; they are not subject to 10 ms
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* d3 to d0 delay required by PCI spec.
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*/
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static void pci_d3delay_fixup(struct pci_dev *dev)
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{
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/*
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* PCI fixups are effectively decided compile time. If we have a dual
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* SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
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*/
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if (!pci_soc_mode)
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return;
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/*
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* True PCI devices in Lincroft should allow type 1 access, the rest
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* are Langwell fake PCI devices.
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*/
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if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
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return;
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dev->d3_delay = 0;
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
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static void mrst_power_off_unused_dev(struct pci_dev *dev)
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{
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pci_set_power_state(dev, PCI_D3hot);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
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/*
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* Langwell devices reside at fixed offsets, don't try to move them.
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*/
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static void pci_fixed_bar_fixup(struct pci_dev *dev)
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{
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unsigned long offset;
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u32 size;
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int i;
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if (!pci_soc_mode)
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return;
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/* Must have extended configuration space */
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if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
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return;
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/* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
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offset = fixed_bar_cap(dev->bus, dev->devfn);
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if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
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PCI_DEVFN(2, 2) == dev->devfn)
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return;
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for (i = 0; i < PCI_ROM_RESOURCE; i++) {
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pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
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dev->resource[i].end = dev->resource[i].start + size - 1;
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dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);
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