230f984662
Now that most platforms don't need disable_fiq and arch_ret_to_user macros, we can remove the empty macros or empty entry-macro.S files. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Jamie Iles <jamie@jamieiles.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ryan Mallon <rmallon@gmail.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com> Acked-by: Shawn Guo <shawn.guo@linaro.org>
42 lines
1.1 KiB
ArmAsm
42 lines
1.1 KiB
ArmAsm
/*
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* arch/arm/mach-ixp4xx/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for IXP4xx-based platforms
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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.macro get_irqnr_preamble, base, tmp
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.endm
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
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ldr \irqstat, [\irqstat] @ get interrupts
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cmp \irqstat, #0
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beq 1001f @ upper IRQ?
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clz \irqnr, \irqstat
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mov \base, #31
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sub \irqnr, \base, \irqnr
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b 1002f @ lower IRQ being
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@ handled
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1001:
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/*
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* IXP465/IXP435 has an upper IRQ status register
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*/
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#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
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ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
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ldr \irqstat, [\irqstat] @ get upper interrupts
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mov \irqnr, #63
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clz \irqstat, \irqstat
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cmp \irqstat, #32
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subne \irqnr, \irqnr, \irqstat
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#endif
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1002:
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.endm
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