0b37e9e8dc
AT91 still uses an offset (0x0100 0000) from the physical address to map the debug UART. This is unfortunate as for some platforms (sama5d3 and earlier), it ends up in the PCI zone and PCI is enabled in multi_v7. Switch to DEBUG_UART_VIRT to solve that. Tested on sama5d3 and 9g20. Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
38 lines
1.1 KiB
ArmAsm
38 lines
1.1 KiB
ArmAsm
/*
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* Copyright (C) 2003-2005 SAN People
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*
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* Debugging macro include header
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#define AT91_DBGU_SR (0x14) /* Status Register */
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#define AT91_DBGU_THR (0x1c) /* Transmitter Holding Register */
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#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
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#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
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.macro addruart, rp, rv, tmp
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ldr \rp, =CONFIG_DEBUG_UART_PHYS @ System peripherals (phys address)
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ldr \rv, =CONFIG_DEBUG_UART_VIRT @ System peripherals (virt address)
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.endm
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.macro senduart,rd,rx
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strb \rd, [\rx, #(AT91_DBGU_THR)] @ Write to Transmitter Holding Register
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.endm
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.macro waituart,rd,rx
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1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
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tst \rd, #AT91_DBGU_TXRDY @ DBGU_TXRDY = 1 when ready to transmit
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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1001: ldr \rd, [\rx, #(AT91_DBGU_SR)] @ Read Status Register
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tst \rd, #AT91_DBGU_TXEMPTY @ DBGU_TXEMPTY = 1 when transmission complete
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beq 1001b
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.endm
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