![Eli Cohen](/assets/img/avatar_default.png)
The driver is comprised of two kernel modules: mlx5_ib and mlx5_core. This partitioning resembles what we have for mlx4, except that mlx5_ib is the pci device driver and not mlx5_core. mlx5_core is essentially a library that provides general functionality that is intended to be used by other Mellanox devices that will be introduced in the future. mlx5_ib has a similar role as any hardware device under drivers/infiniband/hw. Signed-off-by: Eli Cohen <eli@mellanox.com> Signed-off-by: Jack Morgenstein <jackm@dev.mellanox.co.il> Signed-off-by: Or Gerlitz <ogerlitz@mellanox.com> [ Merge in coccinelle fixes from Fengguang Wu <fengguang.wu@intel.com>. - Roland ] Signed-off-by: Roland Dreier <roland@purestorage.com>
166 lines
4.6 KiB
C
166 lines
4.6 KiB
C
/*
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* Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_CORE_CQ_H
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#define MLX5_CORE_CQ_H
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#include <rdma/ib_verbs.h>
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#include <linux/mlx5/driver.h>
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struct mlx5_core_cq {
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u32 cqn;
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int cqe_sz;
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__be32 *set_ci_db;
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__be32 *arm_db;
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atomic_t refcount;
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struct completion free;
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unsigned vector;
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int irqn;
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void (*comp) (struct mlx5_core_cq *);
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void (*event) (struct mlx5_core_cq *, enum mlx5_event);
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struct mlx5_uar *uar;
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u32 cons_index;
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unsigned arm_sn;
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struct mlx5_rsc_debug *dbg;
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int pid;
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};
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enum {
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MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
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MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
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MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
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MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
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MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06,
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MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
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MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
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MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
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MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
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MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
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MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
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MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
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MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
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};
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enum {
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MLX5_CQE_OWNER_MASK = 1,
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MLX5_CQE_REQ = 0,
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MLX5_CQE_RESP_WR_IMM = 1,
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MLX5_CQE_RESP_SEND = 2,
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MLX5_CQE_RESP_SEND_IMM = 3,
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MLX5_CQE_RESP_SEND_INV = 4,
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MLX5_CQE_RESIZE_CQ = 0xff, /* TBD */
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MLX5_CQE_REQ_ERR = 13,
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MLX5_CQE_RESP_ERR = 14,
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};
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enum {
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MLX5_CQ_MODIFY_RESEIZE = 0,
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MLX5_CQ_MODIFY_MODER = 1,
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MLX5_CQ_MODIFY_MAPPING = 2,
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};
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struct mlx5_cq_modify_params {
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int type;
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union {
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struct {
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u32 page_offset;
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u8 log_cq_size;
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} resize;
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struct {
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} moder;
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struct {
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} mapping;
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} params;
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};
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enum {
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CQE_SIZE_64 = 0,
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CQE_SIZE_128 = 1,
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};
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static inline int cqe_sz_to_mlx_sz(u8 size)
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{
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return size == 64 ? CQE_SIZE_64 : CQE_SIZE_128;
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}
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static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq)
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{
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*cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
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}
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enum {
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MLX5_CQ_DB_REQ_NOT_SOL = 1 << 24,
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MLX5_CQ_DB_REQ_NOT = 0 << 24
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};
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static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
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void __iomem *uar_page,
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spinlock_t *doorbell_lock)
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{
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__be32 doorbell[2];
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u32 sn;
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u32 ci;
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sn = cq->arm_sn & 3;
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ci = cq->cons_index & 0xffffff;
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*cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
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/* Make sure that the doorbell record in host memory is
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* written before ringing the doorbell via PCI MMIO.
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*/
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wmb();
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doorbell[0] = cpu_to_be32(sn << 28 | cmd | ci);
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doorbell[1] = cpu_to_be32(cq->cqn);
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mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL, doorbell_lock);
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}
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int mlx5_init_cq_table(struct mlx5_core_dev *dev);
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void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev);
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int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
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struct mlx5_create_cq_mbox_in *in, int inlen);
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int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
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int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
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struct mlx5_query_cq_mbox_out *out);
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int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
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int type, struct mlx5_cq_modify_params *params);
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int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
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void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
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#endif /* MLX5_CORE_CQ_H */
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