![Rob Clark](/assets/img/avatar_default.png)
Add initial support for a3xx 3d core. So far, with hardware that I've seen to date, we can have: + zero, one, or two z180 2d cores + a3xx or a2xx 3d core, which share a common CP (the firmware for the CP seems to implement some different PM4 packet types but the basics of cmdstream submission are the same) Which means that the eventual complete "class" hierarchy, once support for all past and present hw is in place, becomes: + msm_gpu + adreno_gpu + a3xx_gpu + a2xx_gpu + z180_gpu This commit splits out the parts that will eventually be common between a2xx/a3xx into adreno_gpu, and the parts that are even common to z180 into msm_gpu. Note that there is no cmdstream validation required. All memory access from the GPU is via IOMMU/MMU. So as long as you don't map silly things to the GPU, there isn't much damage that the GPU can do. Signed-off-by: Rob Clark <robdclark@gmail.com>
20 lines
445 B
Makefile
20 lines
445 B
Makefile
# UAPI Header export list
|
|
header-y += drm.h
|
|
header-y += drm_fourcc.h
|
|
header-y += drm_mode.h
|
|
header-y += drm_sarea.h
|
|
header-y += exynos_drm.h
|
|
header-y += i810_drm.h
|
|
header-y += i915_drm.h
|
|
header-y += mga_drm.h
|
|
header-y += nouveau_drm.h
|
|
header-y += qxl_drm.h
|
|
header-y += r128_drm.h
|
|
header-y += radeon_drm.h
|
|
header-y += savage_drm.h
|
|
header-y += sis_drm.h
|
|
header-y += tegra_drm.h
|
|
header-y += via_drm.h
|
|
header-y += vmwgfx_drm.h
|
|
header-y += msm_drm.h
|