163 lines
5.4 KiB
Plaintext
163 lines
5.4 KiB
Plaintext
Device-Tree bindings for LVDS Display Bridge (ldb)
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LVDS Display Bridge
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===================
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The LVDS Display Bridge device tree node contains up to two lvds-channel
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nodes describing each of the two LVDS encoder channels of the bridge.
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Required properties:
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- #address-cells : should be <1>
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- #size-cells : should be <0>
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- compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or
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"fsl,imx8qm-ldb".
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All LDB versions are similar.
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i.MX6q/dl has an additional multiplexer in the front to select
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any of the two or four IPU display interfaces as input for each
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LVDS channel.
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i.MX8qm LDB supports 10bit RGB input and needs an additional
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phy.
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- gpr : should be <&gpr> on i.MX53 and i.MX6q.
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The phandle points to the iomuxc-gpr region containing the LVDS
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control register.
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- clocks, clock-names : phandles to the LDB divider and selector clocks and to
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the display interface selector clocks or pixel and
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bypass clocks as described in
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The following clocks are expected on i.MX53:
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"di0_pll" - LDB LVDS channel 0 mux
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"di1_pll" - LDB LVDS channel 1 mux
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"di0" - LDB LVDS channel 0 gate
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"di1" - LDB LVDS channel 1 gate
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"di0_sel" - IPU1 DI0 mux
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"di1_sel" - IPU1 DI1 mux
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On i.MX6q the following additional clocks are needed:
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"di2_sel" - IPU2 DI0 mux
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"di3_sel" - IPU2 DI1 mux
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The following clocks are expected on i.MX8qm:
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"pixel" - pixel clock
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"bypass" - bypass clock
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The needed clock numbers for each are documented in
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Documentation/devicetree/bindings/clock/imx5-clock.txt, and in
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Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in
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Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt.
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- power-domains : phandle pointing to power domain, only required by i.MX8qm.
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Optional properties:
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- pinctrl-names : should be "default" on i.MX53, not used on i.MX6q and i.MX8qm
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- pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
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not used on i.MX6q and i.MX8qm
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- fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
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be configured - one input will be distributed on both outputs in dual
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channel mode
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LVDS Channel
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============
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Each LVDS Channel has to contain either an of graph link to a panel device node
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or a display-timings node that describes the video timings for the connected
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LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
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Required properties:
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- reg : should be <0> or <1>
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- port: Input and output port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/graph.txt.
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On i.MX5, the internal two-input-multiplexer is used. Due to hardware
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limitations, only one input port (port@[0,1]) can be used for each channel
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(lvds-channel@[0,1], respectively).
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On i.MX6, there should be four input ports (port@[0-3]) that correspond
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to the four LVDS multiplexer inputs.
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On i.MX8qm, the two channels of LDB connect to one display interface of DPU.
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A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm)
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must be connected to a panel input port or a bridge input port.
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Optionally, the output port can be left out if display-timings are used
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instead.
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- phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm.
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- phy-names: should be "ldb_phy". Valid only on i.MX8qm.
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Optional properties (required if display-timings are used):
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- ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
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- display-timings : A node that describes the display timings as defined in
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Documentation/devicetree/bindings/display/panel/display-timing.txt.
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- fsl,data-mapping : should be "spwg" or "jeida"
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This describes how the color bits are laid out in the
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serialized LVDS signal.
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- fsl,data-width : should be <18> or <24>
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Additionally, <30> for i.MX8qm.
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example:
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gpr: iomuxc-gpr@53fa8000 {
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/* ... */
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};
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ldb: ldb@53fa8008 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx53-ldb";
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gpr = <&gpr>;
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clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
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<&clks IMX5_CLK_LDB_DI1_SEL>,
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<&clks IMX5_CLK_IPU_DI0_SEL>,
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<&clks IMX5_CLK_IPU_DI1_SEL>,
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<&clks IMX5_CLK_LDB_DI0_GATE>,
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<&clks IMX5_CLK_LDB_DI1_GATE>;
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clock-names = "di0_pll", "di1_pll",
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"di0_sel", "di1_sel",
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"di0", "di1";
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/* Using an of-graph endpoint link to connect the panel */
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lvds-channel@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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port@0 {
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reg = <0>;
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lvds0_in: endpoint {
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remote-endpoint = <&ipu_di0_lvds0>;
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};
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};
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port@2 {
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reg = <2>;
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lvds0_out: endpoint {
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remote-endpoint = <&panel_in>;
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};
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};
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};
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/* Using display-timings and fsl,data-mapping/width instead */
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lvds-channel@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fsl,data-mapping = "spwg";
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fsl,data-width = <24>;
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display-timings {
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/* ... */
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};
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port@1 {
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reg = <1>;
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lvds1_in: endpoint {
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remote-endpoint = <&ipu_di1_lvds1>;
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};
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};
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};
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};
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panel: lvds-panel {
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/* ... */
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port {
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panel_in: endpoint {
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remote-endpoint = <&lvds0_out>;
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};
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};
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};
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